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[92.34.216.5]) by smtp.gmail.com with ESMTPSA id 23-20020ac24857000000b00492c663bba2sm711064lfy.124.2023.04.07.06.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 06:40:20 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Tom Rini , Michael Nazzareno Trimarchi , William Zhang Cc: Anand Gore , Kursad Oney , Joel Peshkin , Philippe Reynes , =?utf-8?b?UmFmYcWCIE1p?= =?utf-8?b?xYJlY2tp?= , Linus Walleij Subject: [PATCH v4 2/5] mtd: rawnand: nand_base: Handle algorithm selection Date: Fri, 7 Apr 2023 15:40:05 +0200 Message-Id: <20230407134008.1939717-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230407134008.1939717-1-linus.walleij@linaro.org> References: <20230407134008.1939717-1-linus.walleij@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Reviewed-by: Michael Trimarchi Acked-by: William Zhang Signed-off-by: Linus Walleij Tested-by: Tom Rini [am335x_evm] --- ChangeLog v3->v4: - After a bug report from Tom, be more careful when assigning algorithm: only overwrite the chip default when something other than undefined was actually detected. ChangeLog v2->v3: - Collect review tags from Michael and William - Resend with the NorthStar enablement patches ChangeLog v1->v2: - Drop pointless check for ecc_algo >= 0, it is always >= 0. --- drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9eba360d55f3..6b4adcf6bdc9 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect); static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { int ret, ecc_mode = -1, ecc_strength, ecc_step; + int ecc_algo = NAND_ECC_UNKNOWN; const char *str; ret = ofnode_read_s32_default(node, "nand-bus-width", -1); @@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod ecc_mode = NAND_ECC_SOFT_BCH; } - if (ecc_mode == NAND_ECC_SOFT) { - str = ofnode_read_string(node, "nand-ecc-algo"); - if (str && !strcmp(str, "bch")) - ecc_mode = NAND_ECC_SOFT_BCH; + str = ofnode_read_string(node, "nand-ecc-algo"); + if (str) { + /* + * If we are in NAND_ECC_SOFT mode, just alter the + * soft mode to BCH here. No change of algorithm. + */ + if (ecc_mode == NAND_ECC_SOFT) { + if (!strcmp(str, "bch")) + ecc_mode = NAND_ECC_SOFT_BCH; + } else { + if (!strcmp(str, "bch")) { + ecc_algo = NAND_ECC_BCH; + } else if (!strcmp(str, "hamming")) { + ecc_algo = NAND_ECC_HAMMING; + } + } } ecc_strength = ofnode_read_s32_default(node, @@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod return -EINVAL; } + /* + * Chip drivers may have assigned default algorithms here, + * onlt override it if we have found something explicitly + * specified in the device tree. + */ + if (ecc_algo != NAND_ECC_UNKNOWN) + chip->ecc.algo = ecc_algo; + if (ecc_mode >= 0) chip->ecc.mode = ecc_mode;