| Message ID | 20230321211312.503812-3-linus.walleij@linaro.org |
|---|---|
| State | Accepted |
| Commit | ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca |
| Headers | show |
| Series | Add Broadcom Northstar basic support | expand |
On Tue, Mar 21, 2023 at 10:13:09PM +0100, Linus Walleij wrote: > For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the > D-Link DIR-885L and DIR-890L routers, we need to explicitly > select the ECC like this in the device tree: > > nand-ecc-algo = "bch"; > nand-ecc-strength = <1>; > nand-ecc-step-size = <512>; > > This is handled by the Linux kernel but U-Boot core does > not respect this. Fix it up by parsing the algorithm and > preserve the behaviour using this property to select > software BCH as far as possible. > > Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> > Acked-by: William Zhang <william.zhang@broadcom.com> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > ChangeLog v2->v3: > - Collect review tags from Michael and William > - Resend with the NorthStar enablement patches > ChangeLog v1->v2: > - Drop pointless check for ecc_algo >= 0, it is always > >= 0. > --- > drivers/mtd/nand/raw/nand_base.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) On am335x_evm, this leads to: CPU : AM335X-GP rev 2.1 Model: TI AM335x EVM DRAM: 1 GiB Core: 156 devices, 17 uclasses, devicetree: separate WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout) NAND: ... hang ... and arch/arm/dts/am335x-evm.dts nand@0,0 describes the chip correctly and worked prior to this change.
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9eba360d55f3..c173fd09237a 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect); static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { int ret, ecc_mode = -1, ecc_strength, ecc_step; + int ecc_algo = NAND_ECC_UNKNOWN; const char *str; ret = ofnode_read_s32_default(node, "nand-bus-width", -1); @@ -4512,10 +4513,13 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod ecc_mode = NAND_ECC_SOFT_BCH; } - if (ecc_mode == NAND_ECC_SOFT) { - str = ofnode_read_string(node, "nand-ecc-algo"); - if (str && !strcmp(str, "bch")) + str = ofnode_read_string(node, "nand-ecc-algo"); + if (str && !strcmp(str, "bch")) { + ecc_algo = NAND_ECC_BCH; + if (ecc_mode == NAND_ECC_SOFT) ecc_mode = NAND_ECC_SOFT_BCH; + } else if (!strcmp(str, "hamming")) { + ecc_algo = NAND_ECC_HAMMING; } ecc_strength = ofnode_read_s32_default(node, @@ -4529,6 +4533,8 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod return -EINVAL; } + chip->ecc.algo = ecc_algo; + if (ecc_mode >= 0) chip->ecc.mode = ecc_mode;