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[85.214.62.61]) by mx.google.com with ESMTPS id p186-20020a1fa6c3000000b0041346bd2bacsi931792vke.293.2023.03.17.09.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 09:23:50 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NuFnyGhF; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C7E1D85A40; Fri, 17 Mar 2023 17:23:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="NuFnyGhF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1EDD885967; Fri, 17 Mar 2023 17:23:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AA84385967 for ; Fri, 17 Mar 2023 17:23:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=paul.liu@linaro.org Received: by mail-pj1-x1031.google.com with SMTP id fy10-20020a17090b020a00b0023b4bcf0727so5779752pjb.0 for ; Fri, 17 Mar 2023 09:23:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679070185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p4+MQ0SCCaSYjeoxRqub4df33kCvVYqWnwAZqQEA/OU=; b=NuFnyGhFkBOn4BnXqhgtxPVSW3qAHYjO+4QNPXcx8vDU7+Q+N5afsQwLRLEZQ8Nd8S uxl90PhHC3sV4uHZG0cKy38Y09s4ny84jSf9+9qKaFxXyhjoNTrqm7IQ7h/4vJlY64Ds R19TdpjfrfFh3L4GDMc4A5lqjOCTYUPdK5QEDY1ckhkZyzNNRoW2pQs7yqKqClwGLjuZ PY/PG9X6CT34kLs+aGrF0iBvze6seYNcKEokiT2AibgRlgEwL69AkDFH/AHnhuhNjUJh r058smRCtKfproptIpjRWDlq9+1rD2iZI3n7szrnd+7xyZBN0Rffoy4f0M2CopWwROU7 94zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679070185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p4+MQ0SCCaSYjeoxRqub4df33kCvVYqWnwAZqQEA/OU=; b=AindFWicZtnviO5enVhkn1xpWRaJPFjLTSEjSB773NWppHm1E7MDidiQiuGO1KQ58A 6xhXsYRduaP1PPN2UnsrbvR6uIAbpfA9x3tX51/J05j3oSHSKzuh38rZPZLNF6VNDdYA ejiB/ChRT6wpt3af8Ul3QLv965LuS/pUj4CY695P5csGIfAn85Y9fodjn/hv3jgtQ1/M 9OdhS+khrrNpYcCn6Vo9GH7A/W9KsZCZsZyuG7ag3ZU9mUBbE2waw7ptaKg081Laosr0 E8aSA/UZ2U2vUYTpJLiMOgr2jQtkAJpb6z/xMxLB6mHQuz/7mQeITGLN+/JKD0zL1AXc vFgQ== X-Gm-Message-State: AO0yUKVAUI16jK+LIdjGaAMYi5NQIseY7gvCe8hzQDJz4gnTOHT0WFLV tNJfXl7mKJoaDodGI8pjmUGo8wFX3vd4d/pGUEE= X-Received: by 2002:a17:90a:1991:b0:237:40a5:7cb9 with SMTP id 17-20020a17090a199100b0023740a57cb9mr8431018pji.5.1679070184659; Fri, 17 Mar 2023 09:23:04 -0700 (PDT) Received: from localhost ([111.184.129.17]) by smtp.gmail.com with ESMTPSA id g8-20020a17090a7d0800b00233ccd04a15sm3282826pjl.24.2023.03.17.09.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 09:23:04 -0700 (PDT) From: "Ying-Chun Liu (PaulLiu)" To: u-boot@lists.denx.de Cc: meitao , Ying-Chun Liu , Tom Rini Subject: [PATCH 3/3] armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present Date: Sat, 18 Mar 2023 00:22:53 +0800 Message-Id: <20230317162253.1049446-4-paul.liu@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230317162253.1049446-1-paul.liu@linaro.org> References: <20230317162253.1049446-1-paul.liu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: meitao u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does. otherwise it will hang when enable mmu, that is what we encounter in our SOC. Signed-off-by: meitao [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f --- arch/arm/cpu/armv8/cache_v8.c | 6 +++++- arch/arm/include/asm/armv8/mmu.h | 10 ++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 4c6a1b1d6c..cb1131a048 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -94,11 +94,15 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; if (gd->arch.has_hafdbs) - tcr |= TCR_HA | TCR_HD; + tcr |= TCR_EL1_HA | TCR_EL1_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL2_HA | TCR_EL2_HD; } else { tcr = TCR_EL3_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL3_HA | TCR_EL3_HD; } /* PTWs cacheable, inner/outer WBWA and inner shareable */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 98a27db316..19a9e112a4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -102,8 +102,14 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) -#define TCR_HA BIT(39) -#define TCR_HD BIT(40) +#define TCR_EL1_HA BIT(39) +#define TCR_EL1_HD BIT(40) + +#define TCR_EL2_HA BIT(21) +#define TCR_EL2_HD BIT(22) + +#define TCR_EL3_HA BIT(21) +#define TCR_EL3_HD BIT(22) #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23)