From patchwork Wed Mar 8 20:26:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ralph Siemsen X-Patchwork-Id: 660468 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp523855wrb; Wed, 8 Mar 2023 12:29:34 -0800 (PST) X-Google-Smtp-Source: AK7set9QdjoiN8Xx7neoKeq/vgrU1X0vnCFPSTQgMCEygTbYP2UDLmI9dc3UTMhmSY9b12CHEdrP X-Received: by 2002:a05:6830:44a2:b0:690:e454:fc1e with SMTP id r34-20020a05683044a200b00690e454fc1emr11639530otv.7.1678307373889; Wed, 08 Mar 2023 12:29:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678307373; cv=none; d=google.com; s=arc-20160816; b=l4lhbOCG1e6tmBhRlSS2Y7E6JjG2vLpdlkRm9Zsa3ZfkMG/EOfgxZG4pkFmuLjLwbz yI/LWcFn2I5rRbzJj8u0qXCuUrXTjPD1BnIUlxHO2kUUMD5jG4uCC3UhSr63gdL5zzv3 sdsjKGpDHLlUjXvlRqfsbOJuB3Vih5zsxhPkYACudFyTpS28sOF3FkgBIneJN50HO1FN rSPLajIZlW/rvhuzlvM8+m/Eh7el/zRqrGIFQ+8IhygiYu2J96Odzub8S32rFqYs7jPI ITN9nTgltsvA2sQdaKjq3TGxo4aprIvvglvajoQ6Ta2erAL016+ctJKkKFYPgHvmettg 8HdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x1RpgKdiVtrDPmWKYXrIP4myheYHdVWwJIxYIvOWMb8=; b=BMgQEgzfrunlVZjRR2q+bu5kd8MTl/bhYit1Q1GOv/mIEO+yUT9nrey33NiuryEsqT JT3UsDbfkEb3cA7zkdiSE25p75On4mwMmHJ1adffVIWZUBVjSNyYMb6SqYYOxCNnIiLM aq9+PnXehKx4zKHfKgBhRW3Zmm7Xq3MbyVxGnFc8gzVjcpwOBmp9z5wFl+X34HBzee4N a1K3hRLA7WEk5extI76fXY3y0oE1ArpsZ5d1Wnw4T9RmFanHMEhmDpjfLnHS2Tmc9hA8 muaYS9FPrttzJAAWK1c+J/hfMgdefKV4nfh96/7SkmqNU3qPnQTy7f6OOdQhABThnhS/ IwCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UAbzk3pK; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id e21-20020a9d0195000000b0068bd234e7bfsi15769969ote.156.2023.03.08.12.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:29:33 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UAbzk3pK; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7079885EE2; Wed, 8 Mar 2023 21:28:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UAbzk3pK"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E800385E99; Wed, 8 Mar 2023 21:27:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x82f.google.com (mail-qt1-x82f.google.com [IPv6:2607:f8b0:4864:20::82f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3F0D285EB3 for ; Wed, 8 Mar 2023 21:27:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ralph.siemsen@linaro.org Received: by mail-qt1-x82f.google.com with SMTP id y10so19542528qtj.2 for ; Wed, 08 Mar 2023 12:27:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678307232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x1RpgKdiVtrDPmWKYXrIP4myheYHdVWwJIxYIvOWMb8=; b=UAbzk3pKZTkVoG+7oW0SEOWuqQoSV9X6ttTCY22USaJmrs2rLknXYYmKstSlCRzfTA wLF1w9vne2at+RTcDaCxt6Lp62zE4rFeGNir2ZgrckMGy+J99U8Rn52lzoltP3ZtKJmb pXsNaGFDxyLQ8PhK5j3GWrHXRIAnw34RI+ddWaiyoUiBqRqW1HUuFUrC9cU86+WgEsto 1DLcr3/iFk/elS+qh8H+2CnLfIbCN86ts/HsNh9eJs6mKtshj/TToaoyf54pTgLGc3mS b2PIq6TBqqIKYDwjHuPtEySmcr4JegOWfPVM8tk7xRkf8zgDJAUySco0d+EpThm+4/w4 nZng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678307232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x1RpgKdiVtrDPmWKYXrIP4myheYHdVWwJIxYIvOWMb8=; b=EFt5eg+QTSc7o9H9t6wL795BDWsfoPHgUiGi+mmUxC4vhr8pKVM+IQ7oM2yjEi8AHF NBwg9NcsBbGJkccl1GKpVDzMzvBL2JVam4QF85qFTiiNNPCjPfxpdcj+J9AVqrVgLoP5 eENdN42K1oVqXi0i1T5uqwWXaKP0p53UBSX5ALoyPn6TE9/lqFJPOIgRmI9MualTuzI9 jG6tX+13fzuDYc/FYd9cLNpvkBwwHCMdu24wJYCwDUGkVNcuDS4PftxcKd2Z7bf4P7EK MNiGTG2ttSUocOwUaS9Xen95KSDg4yxQ2oyjU53UbtOfXu1B4b53j/UFZ3sSiR3mJyxN J7RQ== X-Gm-Message-State: AO0yUKWeKmJ0c3F8UilFNHaIrkA8izpgI/9heQozphF+FZ4b7lOsS+PW FaGhOGx/GfDEXbiii4XRa9juqSTE3hYlDQGvhyXZ6Q== X-Received: by 2002:ac8:57c4:0:b0:3bd:1a07:2086 with SMTP id w4-20020ac857c4000000b003bd1a072086mr1371288qta.36.1678307231692; Wed, 08 Mar 2023 12:27:11 -0800 (PST) Received: from maple.netwinder.org (rfs.netwinder.org. [206.248.184.2]) by smtp.gmail.com with ESMTPSA id m2-20020ac84442000000b003b86b088755sm12144203qtn.15.2023.03.08.12.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:27:11 -0800 (PST) From: Ralph Siemsen To: u-boot@lists.denx.de Cc: Marek Vasut , Ralph Siemsen , Chris Packham Subject: [PATCH v4 08/10] board: schneider: add RZN1 board support Date: Wed, 8 Mar 2023 15:26:51 -0500 Message-Id: <20230308202653.1926303-9-ralph.siemsen@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308202653.1926303-1-ralph.siemsen@linaro.org> References: <20230308202653.1926303-1-ralph.siemsen@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen --- Changes in v4: - add binman support via r9a06g032-rzn1-snarc-u-boot.dtsi Changes in v3: - rename board LCES to rzn1-snarc - move CONFIG_SYS_NS16550_MEM32 to Kconfig - define CFG_SYS_INIT_RAM_{ADDR,SIZE} - removed debug uart settings from defconfig arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi | 23 + arch/arm/dts/r9a06g032-rzn1-snarc.dts | 51 +++ arch/arm/mach-rzn1/Kconfig | 14 + board/schneider/rzn1-snarc/Kconfig | 18 + board/schneider/rzn1-snarc/Makefile | 3 + board/schneider/rzn1-snarc/ddr_timing.c | 140 ++++++ .../jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++++++++++++++++++ board/schneider/rzn1-snarc/rzn1.c | 39 ++ configs/rzn1_snarc_defconfig | 21 + include/configs/rzn1-snarc.h | 17 + 10 files changed, 725 insertions(+) create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi create mode 100644 arch/arm/dts/r9a06g032-rzn1-snarc.dts create mode 100644 board/schneider/rzn1-snarc/Kconfig create mode 100644 board/schneider/rzn1-snarc/Makefile create mode 100644 board/schneider/rzn1-snarc/ddr_timing.c create mode 100644 board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/rzn1-snarc/rzn1.c create mode 100644 configs/rzn1_snarc_defconfig create mode 100644 include/configs/rzn1-snarc.h diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi new file mode 100644 index 0000000000..794e711103 --- /dev/null +++ b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Configuration file for binman + * + * After building u-boot, can generate the SPKG output by running: + * tools/binman/binman build -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -O + */ + +#include + +/ { + binman: binman { + }; +}; + +&binman { + mkimage { + filename = "u-boot.bin.spkg"; + args = "-n board/schneider/rzn1-snarc/spkgimage.cfg -T spkgimage -a 0x20040000 -e 0x20040000"; + u-boot { + }; + }; +}; diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts new file mode 100644 index 0000000000..abb269cc21 --- /dev/null +++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Schneider RZ/N1 Board + * + * Based on r9a06g032-rzn1d400-db.dts + */ + +/dts-v1/; + +#include "r9a06g032.dtsi" +#include + +/ { + model = "Schneider RZ/N1 Board"; + compatible = "schneider,rzn1", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&ddrctrl { + status = "okay"; +}; + +&pinctrl { + status = "okay"; + + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + bias-disable; + }; +}; + +&uart0 { + pinctrl-0 = <&pins_uart0>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig index 707895874d..4b13afbb32 100644 --- a/arch/arm/mach-rzn1/Kconfig +++ b/arch/arm/mach-rzn1/Kconfig @@ -15,4 +15,18 @@ endchoice config SYS_SOC default "rzn1" +choice + prompt "Board select" + default TARGET_SCHNEIDER_RZN1 + +config TARGET_SCHNEIDER_RZN1 + bool "Schneider RZN1 board" + help + Support the Schneider RZN1D and RZN1S boards, which are based + on the Renesas RZ/N1 SoC. + +endchoice + +source "board/schneider/rzn1-snarc/Kconfig" + endif diff --git a/board/schneider/rzn1-snarc/Kconfig b/board/schneider/rzn1-snarc/Kconfig new file mode 100644 index 0000000000..bb6d394077 --- /dev/null +++ b/board/schneider/rzn1-snarc/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SCHNEIDER_RZN1 + +config TEXT_BASE + default 0x20040000 if ARCH_RZN1 + +config SYS_MONITOR_LEN + default 524288 if ARCH_RZN1 + +config SYS_BOARD + default "rzn1-snarc" + +config SYS_VENDOR + default "schneider" + +config SYS_CONFIG_NAME + default "rzn1-snarc" + +endif diff --git a/board/schneider/rzn1-snarc/Makefile b/board/schneider/rzn1-snarc/Makefile new file mode 100644 index 0000000000..95c151898b --- /dev/null +++ b/board/schneider/rzn1-snarc/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := rzn1.o ddr_timing.o diff --git a/board/schneider/rzn1-snarc/ddr_timing.c b/board/schneider/rzn1-snarc/ddr_timing.c new file mode 100644 index 0000000000..8bc3fe7be4 --- /dev/null +++ b/board/schneider/rzn1-snarc/ddr_timing.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include "jedec_ddr3_2g_x16_1333h_500_cl8.h" + +u32 ddr_00_87_async[] = { + DENALI_CTL_00_DATA, + DENALI_CTL_01_DATA, + DENALI_CTL_02_DATA, + DENALI_CTL_03_DATA, + DENALI_CTL_04_DATA, + DENALI_CTL_05_DATA, + DENALI_CTL_06_DATA, + DENALI_CTL_07_DATA, + DENALI_CTL_08_DATA, + DENALI_CTL_09_DATA, + + DENALI_CTL_10_DATA, + DENALI_CTL_11_DATA, + DENALI_CTL_12_DATA, + DENALI_CTL_13_DATA, + DENALI_CTL_14_DATA, + DENALI_CTL_15_DATA, + DENALI_CTL_16_DATA, + DENALI_CTL_17_DATA, + DENALI_CTL_18_DATA, + DENALI_CTL_19_DATA, + + DENALI_CTL_20_DATA, + DENALI_CTL_21_DATA, + DENALI_CTL_22_DATA, + DENALI_CTL_23_DATA, + DENALI_CTL_24_DATA, + DENALI_CTL_25_DATA, + DENALI_CTL_26_DATA, + DENALI_CTL_27_DATA, + DENALI_CTL_28_DATA, + DENALI_CTL_29_DATA, + + DENALI_CTL_30_DATA, + DENALI_CTL_31_DATA, + DENALI_CTL_32_DATA, + DENALI_CTL_33_DATA, + DENALI_CTL_34_DATA, + DENALI_CTL_35_DATA, + DENALI_CTL_36_DATA, + DENALI_CTL_37_DATA, + DENALI_CTL_38_DATA, + DENALI_CTL_39_DATA, + + DENALI_CTL_40_DATA, + DENALI_CTL_41_DATA, + DENALI_CTL_42_DATA, + DENALI_CTL_43_DATA, + DENALI_CTL_44_DATA, + DENALI_CTL_45_DATA, + DENALI_CTL_46_DATA, + DENALI_CTL_47_DATA, + DENALI_CTL_48_DATA, + DENALI_CTL_49_DATA, + + DENALI_CTL_50_DATA, + DENALI_CTL_51_DATA, + DENALI_CTL_52_DATA, + DENALI_CTL_53_DATA, + DENALI_CTL_54_DATA, + DENALI_CTL_55_DATA, + DENALI_CTL_56_DATA, + DENALI_CTL_57_DATA, + DENALI_CTL_58_DATA, + DENALI_CTL_59_DATA, + + DENALI_CTL_60_DATA, + DENALI_CTL_61_DATA, + DENALI_CTL_62_DATA, + DENALI_CTL_63_DATA, + DENALI_CTL_64_DATA, + DENALI_CTL_65_DATA, + DENALI_CTL_66_DATA, + DENALI_CTL_67_DATA, + DENALI_CTL_68_DATA, + DENALI_CTL_69_DATA, + + DENALI_CTL_70_DATA, + DENALI_CTL_71_DATA, + DENALI_CTL_72_DATA, + DENALI_CTL_73_DATA, + DENALI_CTL_74_DATA, + DENALI_CTL_75_DATA, + DENALI_CTL_76_DATA, + DENALI_CTL_77_DATA, + DENALI_CTL_78_DATA, + DENALI_CTL_79_DATA, + + DENALI_CTL_80_DATA, + DENALI_CTL_81_DATA, + DENALI_CTL_82_DATA, + DENALI_CTL_83_DATA, + DENALI_CTL_84_DATA, + DENALI_CTL_85_DATA, + DENALI_CTL_86_DATA, + DENALI_CTL_87_DATA, + DENALI_CTL_88_DATA, + DENALI_CTL_89_DATA, + + DENALI_CTL_90_DATA, + DENALI_CTL_91_DATA, + DENALI_CTL_92_DATA, +}; + +u32 ddr_350_374_async[] = { + DENALI_CTL_350_DATA, + DENALI_CTL_351_DATA, + DENALI_CTL_352_DATA, + DENALI_CTL_353_DATA, + DENALI_CTL_354_DATA, + DENALI_CTL_355_DATA, + DENALI_CTL_356_DATA, + DENALI_CTL_357_DATA, + DENALI_CTL_358_DATA, + DENALI_CTL_359_DATA, + + DENALI_CTL_360_DATA, + DENALI_CTL_361_DATA, + DENALI_CTL_362_DATA, + DENALI_CTL_363_DATA, + DENALI_CTL_364_DATA, + DENALI_CTL_365_DATA, + DENALI_CTL_366_DATA, + DENALI_CTL_367_DATA, + DENALI_CTL_368_DATA, + DENALI_CTL_369_DATA, + + DENALI_CTL_370_DATA, + DENALI_CTL_371_DATA, + DENALI_CTL_372_DATA, + DENALI_CTL_373_DATA, + DENALI_CTL_374_DATA, +}; diff --git a/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h b/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h new file mode 100644 index 0000000000..5c55518bc1 --- /dev/null +++ b/board/schneider/rzn1-snarc/jedec_ddr3_2g_x16_1333h_500_cl8.h @@ -0,0 +1,399 @@ + +/* **************************************************************** + * CADENCE Copyright (c) 2001-2011 * + * Cadence Design Systems, Inc. * + * All rights reserved. * + * * + ****************************************************************** + * The values calculated from this script are meant to be * + * representative programmings. The values may not reflect the * + * actual required programming for production use. Please * + * closely review all programmed values for technical accuracy * + * before use in production parts. * + ****************************************************************** + * + * Module: regconfig.h + * Documentation: Register programming header file + * + ****************************************************************** + ****************************************************************** + * WARNING: This file was automatically generated. Manual + * editing may result in undetermined behavior. + ****************************************************************** + ******************************************************************/ + +#define DENALI_CTL_00_DATA 0x00000600 +#define DENALI_CTL_01_DATA 0x00000000 +#define DENALI_CTL_02_DATA 0x00000000 +#define DENALI_CTL_03_DATA 0x00000000 +#define DENALI_CTL_04_DATA 0x00000000 +#define DENALI_CTL_05_DATA 0x00000000 +#define DENALI_CTL_06_DATA 0x00000000 +#define DENALI_CTL_07_DATA 0x00000005 +#define DENALI_CTL_08_DATA 0x000186a0 +#define DENALI_CTL_09_DATA 0x0003d090 +#define DENALI_CTL_10_DATA 0x00000000 +#define DENALI_CTL_11_DATA 0x10000200 +#define DENALI_CTL_12_DATA 0x04040006 +#define DENALI_CTL_13_DATA 0x04121904 +#define DENALI_CTL_14_DATA 0x04041707 +#define DENALI_CTL_15_DATA 0x00891c0c +#define DENALI_CTL_16_DATA 0x07000503 +#define DENALI_CTL_17_DATA 0x01010008 +#define DENALI_CTL_18_DATA 0x0007030f +#define DENALI_CTL_19_DATA 0x01000000 +#define DENALI_CTL_20_DATA 0x0f340050 +#define DENALI_CTL_21_DATA 0x00000005 +#define DENALI_CTL_22_DATA 0x000c0003 +#define DENALI_CTL_23_DATA 0x00000000 +#define DENALI_CTL_24_DATA 0x00550200 +#define DENALI_CTL_25_DATA 0x00010000 +#define DENALI_CTL_26_DATA 0x00050500 +#define DENALI_CTL_27_DATA 0x00000000 +#define DENALI_CTL_28_DATA 0x00000000 +#define DENALI_CTL_29_DATA 0x00000000 +#define DENALI_CTL_30_DATA 0x00000000 +#define DENALI_CTL_31_DATA 0x00084000 +#define DENALI_CTL_32_DATA 0x00080046 +#define DENALI_CTL_33_DATA 0x00000000 +#define DENALI_CTL_34_DATA 0x00460840 +#define DENALI_CTL_35_DATA 0x00000008 +#define DENALI_CTL_36_DATA 0x00010000 +#define DENALI_CTL_37_DATA 0x00000000 +#define DENALI_CTL_38_DATA 0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 +#define DENALI_CTL_40_DATA 0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 +#define DENALI_CTL_43_DATA 0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 +#define DENALI_CTL_45_DATA 0x01000200 +#define DENALI_CTL_46_DATA 0x02000040 +#define DENALI_CTL_47_DATA 0x00000040 +#define DENALI_CTL_48_DATA 0x02000100 +#define DENALI_CTL_49_DATA 0xffff0a01 +#define DENALI_CTL_50_DATA 0x01010101 +#define DENALI_CTL_51_DATA 0x01010101 +#define DENALI_CTL_52_DATA 0x01030101 +#define DENALI_CTL_53_DATA 0x0c030000 +#define DENALI_CTL_54_DATA 0x00000000 +#define DENALI_CTL_55_DATA 0x00000100 +#define DENALI_CTL_56_DATA 0x00000000 +#define DENALI_CTL_57_DATA 0x00000000 +#define DENALI_CTL_58_DATA 0x00000000 +#define DENALI_CTL_59_DATA 0x00000000 +#define DENALI_CTL_60_DATA 0x00000000 +#define DENALI_CTL_61_DATA 0x00000000 +#define DENALI_CTL_62_DATA 0x01020000 +#define DENALI_CTL_63_DATA 0x06050201 +#define DENALI_CTL_64_DATA 0x02000106 +#define DENALI_CTL_65_DATA 0x00000000 +#define DENALI_CTL_66_DATA 0x02020202 +#define DENALI_CTL_67_DATA 0x00000200 +#define DENALI_CTL_68_DATA 0x00000000 +#define DENALI_CTL_69_DATA 0x00000000 +#define DENALI_CTL_70_DATA 0x00000000 +#define DENALI_CTL_71_DATA 0x00280d00 +#define DENALI_CTL_72_DATA 0x00000000 +#define DENALI_CTL_73_DATA 0x00000100 +#define DENALI_CTL_74_DATA 0x00010001 +#define DENALI_CTL_75_DATA 0x00000000 +#define DENALI_CTL_76_DATA 0x00000000 +#define DENALI_CTL_77_DATA 0x00000000 +#define DENALI_CTL_78_DATA 0x00000000 +#define DENALI_CTL_79_DATA 0x00222200 +#define DENALI_CTL_80_DATA 0x00000001 +#define DENALI_CTL_81_DATA 0x00000000 +#define DENALI_CTL_82_DATA 0x00000000 +#define DENALI_CTL_83_DATA 0x00012222 +#define DENALI_CTL_84_DATA 0x00000000 +#define DENALI_CTL_85_DATA 0x00000000 +#define DENALI_CTL_86_DATA 0x00222200 +#define DENALI_CTL_87_DATA 0x02020001 +#define DENALI_CTL_88_DATA 0x00020200 +#define DENALI_CTL_89_DATA 0x02000202 +#define DENALI_CTL_90_DATA 0x01000002 +#define DENALI_CTL_91_DATA 0x00000000 +#define DENALI_CTL_92_DATA 0x0003ffff +#define DENALI_CTL_93_DATA 0x00000000 +#define DENALI_CTL_94_DATA 0x0003ffff +#define DENALI_CTL_95_DATA 0x00000000 +#define DENALI_CTL_96_DATA 0x0003ffff +#define DENALI_CTL_97_DATA 0x00000000 +#define DENALI_CTL_98_DATA 0x0003ffff +#define DENALI_CTL_99_DATA 0x00000000 +#define DENALI_CTL_100_DATA 0x0003ffff +#define DENALI_CTL_101_DATA 0x00000000 +#define DENALI_CTL_102_DATA 0x0003ffff +#define DENALI_CTL_103_DATA 0x00000000 +#define DENALI_CTL_104_DATA 0x0003ffff +#define DENALI_CTL_105_DATA 0x00000000 +#define DENALI_CTL_106_DATA 0x0003ffff +#define DENALI_CTL_107_DATA 0x00000000 +#define DENALI_CTL_108_DATA 0x0003ffff +#define DENALI_CTL_109_DATA 0x00000000 +#define DENALI_CTL_110_DATA 0x0003ffff +#define DENALI_CTL_111_DATA 0x00000000 +#define DENALI_CTL_112_DATA 0x0003ffff +#define DENALI_CTL_113_DATA 0x00000000 +#define DENALI_CTL_114_DATA 0x0003ffff +#define DENALI_CTL_115_DATA 0x00000000 +#define DENALI_CTL_116_DATA 0x0003ffff +#define DENALI_CTL_117_DATA 0x00000000 +#define DENALI_CTL_118_DATA 0x0003ffff +#define DENALI_CTL_119_DATA 0x00000000 +#define DENALI_CTL_120_DATA 0x0003ffff +#define DENALI_CTL_121_DATA 0x00000000 +#define DENALI_CTL_122_DATA 0x0003ffff +#define DENALI_CTL_123_DATA 0x00000000 +#define DENALI_CTL_124_DATA 0x0003ffff +#define DENALI_CTL_125_DATA 0x00000000 +#define DENALI_CTL_126_DATA 0x0003ffff +#define DENALI_CTL_127_DATA 0x00000000 +#define DENALI_CTL_128_DATA 0x0003ffff +#define DENALI_CTL_129_DATA 0x00000000 +#define DENALI_CTL_130_DATA 0x0003ffff +#define DENALI_CTL_131_DATA 0x00000000 +#define DENALI_CTL_132_DATA 0x0003ffff +#define DENALI_CTL_133_DATA 0x00000000 +#define DENALI_CTL_134_DATA 0x0003ffff +#define DENALI_CTL_135_DATA 0x00000000 +#define DENALI_CTL_136_DATA 0x0003ffff +#define DENALI_CTL_137_DATA 0x00000000 +#define DENALI_CTL_138_DATA 0x0003ffff +#define DENALI_CTL_139_DATA 0x00000000 +#define DENALI_CTL_140_DATA 0x0003ffff +#define DENALI_CTL_141_DATA 0x00000000 +#define DENALI_CTL_142_DATA 0x0003ffff +#define DENALI_CTL_143_DATA 0x00000000 +#define DENALI_CTL_144_DATA 0x0003ffff +#define DENALI_CTL_145_DATA 0x00000000 +#define DENALI_CTL_146_DATA 0x0003ffff +#define DENALI_CTL_147_DATA 0x00000000 +#define DENALI_CTL_148_DATA 0x0003ffff +#define DENALI_CTL_149_DATA 0x00000000 +#define DENALI_CTL_150_DATA 0x0003ffff +#define DENALI_CTL_151_DATA 0x00000000 +#define DENALI_CTL_152_DATA 0x0003ffff +#define DENALI_CTL_153_DATA 0x00000000 +#define DENALI_CTL_154_DATA 0x0003ffff +#define DENALI_CTL_155_DATA 0x00000000 +#define DENALI_CTL_156_DATA 0x0003ffff +#define DENALI_CTL_157_DATA 0x00000000 +#define DENALI_CTL_158_DATA 0x0003ffff +#define DENALI_CTL_159_DATA 0x00000000 +#define DENALI_CTL_160_DATA 0x0003ffff +#define DENALI_CTL_161_DATA 0x00000000 +#define DENALI_CTL_162_DATA 0x0003ffff +#define DENALI_CTL_163_DATA 0x00000000 +#define DENALI_CTL_164_DATA 0x0003ffff +#define DENALI_CTL_165_DATA 0x00000000 +#define DENALI_CTL_166_DATA 0x0003ffff +#define DENALI_CTL_167_DATA 0x00000000 +#define DENALI_CTL_168_DATA 0x0003ffff +#define DENALI_CTL_169_DATA 0x00000000 +#define DENALI_CTL_170_DATA 0x0003ffff +#define DENALI_CTL_171_DATA 0x00000000 +#define DENALI_CTL_172_DATA 0x0003ffff +#define DENALI_CTL_173_DATA 0x00000000 +#define DENALI_CTL_174_DATA 0x0003ffff +#define DENALI_CTL_175_DATA 0x00000000 +#define DENALI_CTL_176_DATA 0x0003ffff +#define DENALI_CTL_177_DATA 0x00000000 +#define DENALI_CTL_178_DATA 0x0003ffff +#define DENALI_CTL_179_DATA 0x00000000 +#define DENALI_CTL_180_DATA 0x0003ffff +#define DENALI_CTL_181_DATA 0x00000000 +#define DENALI_CTL_182_DATA 0x0003ffff +#define DENALI_CTL_183_DATA 0x00000000 +#define DENALI_CTL_184_DATA 0x0003ffff +#define DENALI_CTL_185_DATA 0x00000000 +#define DENALI_CTL_186_DATA 0x0003ffff +#define DENALI_CTL_187_DATA 0x00000000 +#define DENALI_CTL_188_DATA 0x0003ffff +#define DENALI_CTL_189_DATA 0x00000000 +#define DENALI_CTL_190_DATA 0x0003ffff +#define DENALI_CTL_191_DATA 0x00000000 +#define DENALI_CTL_192_DATA 0x0003ffff +#define DENALI_CTL_193_DATA 0x00000000 +#define DENALI_CTL_194_DATA 0x0003ffff +#define DENALI_CTL_195_DATA 0x00000000 +#define DENALI_CTL_196_DATA 0x0003ffff +#define DENALI_CTL_197_DATA 0x00000000 +#define DENALI_CTL_198_DATA 0x0003ffff +#define DENALI_CTL_199_DATA 0x00000000 +#define DENALI_CTL_200_DATA 0x0003ffff +#define DENALI_CTL_201_DATA 0x00000000 +#define DENALI_CTL_202_DATA 0x0003ffff +#define DENALI_CTL_203_DATA 0x00000000 +#define DENALI_CTL_204_DATA 0x0003ffff +#define DENALI_CTL_205_DATA 0x00000000 +#define DENALI_CTL_206_DATA 0x0003ffff +#define DENALI_CTL_207_DATA 0x00000000 +#define DENALI_CTL_208_DATA 0x0003ffff +#define DENALI_CTL_209_DATA 0x00000000 +#define DENALI_CTL_210_DATA 0x0003ffff +#define DENALI_CTL_211_DATA 0x00000000 +#define DENALI_CTL_212_DATA 0x0003ffff +#define DENALI_CTL_213_DATA 0x00000000 +#define DENALI_CTL_214_DATA 0x0003ffff +#define DENALI_CTL_215_DATA 0x00000000 +#define DENALI_CTL_216_DATA 0x0003ffff +#define DENALI_CTL_217_DATA 0x00000000 +#define DENALI_CTL_218_DATA 0x0303ffff +#define DENALI_CTL_219_DATA 0xffffffff +#define DENALI_CTL_220_DATA 0x00030f0f +#define DENALI_CTL_221_DATA 0xffffffff +#define DENALI_CTL_222_DATA 0x00030f0f +#define DENALI_CTL_223_DATA 0xffffffff +#define DENALI_CTL_224_DATA 0x00030f0f +#define DENALI_CTL_225_DATA 0xffffffff +#define DENALI_CTL_226_DATA 0x00030f0f +#define DENALI_CTL_227_DATA 0xffffffff +#define DENALI_CTL_228_DATA 0x00030f0f +#define DENALI_CTL_229_DATA 0xffffffff +#define DENALI_CTL_230_DATA 0x00030f0f +#define DENALI_CTL_231_DATA 0xffffffff +#define DENALI_CTL_232_DATA 0x00030f0f +#define DENALI_CTL_233_DATA 0xffffffff +#define DENALI_CTL_234_DATA 0x00030f0f +#define DENALI_CTL_235_DATA 0xffffffff +#define DENALI_CTL_236_DATA 0x00030f0f +#define DENALI_CTL_237_DATA 0xffffffff +#define DENALI_CTL_238_DATA 0x00030f0f +#define DENALI_CTL_239_DATA 0xffffffff +#define DENALI_CTL_240_DATA 0x00030f0f +#define DENALI_CTL_241_DATA 0xffffffff +#define DENALI_CTL_242_DATA 0x00030f0f +#define DENALI_CTL_243_DATA 0xffffffff +#define DENALI_CTL_244_DATA 0x00030f0f +#define DENALI_CTL_245_DATA 0xffffffff +#define DENALI_CTL_246_DATA 0x00030f0f +#define DENALI_CTL_247_DATA 0xffffffff +#define DENALI_CTL_248_DATA 0x00030f0f +#define DENALI_CTL_249_DATA 0xffffffff +#define DENALI_CTL_250_DATA 0x00030f0f +#define DENALI_CTL_251_DATA 0xffffffff +#define DENALI_CTL_252_DATA 0x00030f0f +#define DENALI_CTL_253_DATA 0xffffffff +#define DENALI_CTL_254_DATA 0x00030f0f +#define DENALI_CTL_255_DATA 0xffffffff +#define DENALI_CTL_256_DATA 0x00030f0f +#define DENALI_CTL_257_DATA 0xffffffff +#define DENALI_CTL_258_DATA 0x00030f0f +#define DENALI_CTL_259_DATA 0xffffffff +#define DENALI_CTL_260_DATA 0x00030f0f +#define DENALI_CTL_261_DATA 0xffffffff +#define DENALI_CTL_262_DATA 0x00030f0f +#define DENALI_CTL_263_DATA 0xffffffff +#define DENALI_CTL_264_DATA 0x00030f0f +#define DENALI_CTL_265_DATA 0xffffffff +#define DENALI_CTL_266_DATA 0x00030f0f +#define DENALI_CTL_267_DATA 0xffffffff +#define DENALI_CTL_268_DATA 0x00030f0f +#define DENALI_CTL_269_DATA 0xffffffff +#define DENALI_CTL_270_DATA 0x00030f0f +#define DENALI_CTL_271_DATA 0xffffffff +#define DENALI_CTL_272_DATA 0x00030f0f +#define DENALI_CTL_273_DATA 0xffffffff +#define DENALI_CTL_274_DATA 0x00030f0f +#define DENALI_CTL_275_DATA 0xffffffff +#define DENALI_CTL_276_DATA 0x00030f0f +#define DENALI_CTL_277_DATA 0xffffffff +#define DENALI_CTL_278_DATA 0x00030f0f +#define DENALI_CTL_279_DATA 0xffffffff +#define DENALI_CTL_280_DATA 0x00030f0f +#define DENALI_CTL_281_DATA 0xffffffff +#define DENALI_CTL_282_DATA 0x00030f0f +#define DENALI_CTL_283_DATA 0xffffffff +#define DENALI_CTL_284_DATA 0x00030f0f +#define DENALI_CTL_285_DATA 0xffffffff +#define DENALI_CTL_286_DATA 0x00030f0f +#define DENALI_CTL_287_DATA 0xffffffff +#define DENALI_CTL_288_DATA 0x00030f0f +#define DENALI_CTL_289_DATA 0xffffffff +#define DENALI_CTL_290_DATA 0x00030f0f +#define DENALI_CTL_291_DATA 0xffffffff +#define DENALI_CTL_292_DATA 0x00030f0f +#define DENALI_CTL_293_DATA 0xffffffff +#define DENALI_CTL_294_DATA 0x00030f0f +#define DENALI_CTL_295_DATA 0xffffffff +#define DENALI_CTL_296_DATA 0x00030f0f +#define DENALI_CTL_297_DATA 0xffffffff +#define DENALI_CTL_298_DATA 0x00030f0f +#define DENALI_CTL_299_DATA 0xffffffff +#define DENALI_CTL_300_DATA 0x00030f0f +#define DENALI_CTL_301_DATA 0xffffffff +#define DENALI_CTL_302_DATA 0x00030f0f +#define DENALI_CTL_303_DATA 0xffffffff +#define DENALI_CTL_304_DATA 0x00030f0f +#define DENALI_CTL_305_DATA 0xffffffff +#define DENALI_CTL_306_DATA 0x00030f0f +#define DENALI_CTL_307_DATA 0xffffffff +#define DENALI_CTL_308_DATA 0x00030f0f +#define DENALI_CTL_309_DATA 0xffffffff +#define DENALI_CTL_310_DATA 0x00030f0f +#define DENALI_CTL_311_DATA 0xffffffff +#define DENALI_CTL_312_DATA 0x00030f0f +#define DENALI_CTL_313_DATA 0xffffffff +#define DENALI_CTL_314_DATA 0x00030f0f +#define DENALI_CTL_315_DATA 0xffffffff +#define DENALI_CTL_316_DATA 0x00030f0f +#define DENALI_CTL_317_DATA 0xffffffff +#define DENALI_CTL_318_DATA 0x00030f0f +#define DENALI_CTL_319_DATA 0xffffffff +#define DENALI_CTL_320_DATA 0x00030f0f +#define DENALI_CTL_321_DATA 0xffffffff +#define DENALI_CTL_322_DATA 0x00030f0f +#define DENALI_CTL_323_DATA 0xffffffff +#define DENALI_CTL_324_DATA 0x00030f0f +#define DENALI_CTL_325_DATA 0xffffffff +#define DENALI_CTL_326_DATA 0x00030f0f +#define DENALI_CTL_327_DATA 0xffffffff +#define DENALI_CTL_328_DATA 0x00030f0f +#define DENALI_CTL_329_DATA 0xffffffff +#define DENALI_CTL_330_DATA 0x00030f0f +#define DENALI_CTL_331_DATA 0xffffffff +#define DENALI_CTL_332_DATA 0x00030f0f +#define DENALI_CTL_333_DATA 0xffffffff +#define DENALI_CTL_334_DATA 0x00030f0f +#define DENALI_CTL_335_DATA 0xffffffff +#define DENALI_CTL_336_DATA 0x00030f0f +#define DENALI_CTL_337_DATA 0xffffffff +#define DENALI_CTL_338_DATA 0x00030f0f +#define DENALI_CTL_339_DATA 0xffffffff +#define DENALI_CTL_340_DATA 0x00030f0f +#define DENALI_CTL_341_DATA 0xffffffff +#define DENALI_CTL_342_DATA 0x00030f0f +#define DENALI_CTL_343_DATA 0xffffffff +#define DENALI_CTL_344_DATA 0x00030f0f +#define DENALI_CTL_345_DATA 0xffffffff +#define DENALI_CTL_346_DATA 0x32030f0f +#define DENALI_CTL_347_DATA 0x01320001 +#define DENALI_CTL_348_DATA 0x00013200 +#define DENALI_CTL_349_DATA 0x00000132 +#define DENALI_CTL_350_DATA 0x00000000 +#define DENALI_CTL_351_DATA 0x000d0000 +#define DENALI_CTL_352_DATA 0x1e680000 +#define DENALI_CTL_353_DATA 0x02000200 +#define DENALI_CTL_354_DATA 0x02000200 +#define DENALI_CTL_355_DATA 0x00001e68 +#define DENALI_CTL_356_DATA 0x00009808 +#define DENALI_CTL_357_DATA 0x00020608 +#define DENALI_CTL_358_DATA 0x000a0a01 +#define DENALI_CTL_359_DATA 0x00000000 +#define DENALI_CTL_360_DATA 0x00000000 +#define DENALI_CTL_361_DATA 0x04038000 +#define DENALI_CTL_362_DATA 0x07030a07 +#define DENALI_CTL_363_DATA 0x00ffff22 +#define DENALI_CTL_364_DATA 0x000f0010 +#define DENALI_CTL_365_DATA 0x00000000 +#define DENALI_CTL_366_DATA 0x00000000 +#define DENALI_CTL_367_DATA 0x00000000 +#define DENALI_CTL_368_DATA 0x00000000 +#define DENALI_CTL_369_DATA 0x00000000 +#define DENALI_CTL_370_DATA 0x00000204 +#define DENALI_CTL_371_DATA 0x00000000 +#define DENALI_CTL_372_DATA 0x01000001 +#define DENALI_CTL_373_DATA 0x00000001 +#define DENALI_CTL_374_DATA 0x00000000 diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c new file mode 100644 index 0000000000..a6cb21822f --- /dev/null +++ b/board/schneider/rzn1-snarc/rzn1.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + struct udevice *dev; + int err; + + /* This will end up calling cadence_ddr_probe() */ + err = uclass_get_device(UCLASS_RAM, 0, &dev); + if (err) { + debug("DRAM init failed: %d\n", err); + return err; + } + + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig new file mode 100644 index 0000000000..f0df13bcd9 --- /dev/null +++ b/configs/rzn1_snarc_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_RZN1=y +CONFIG_SYS_MALLOC_LEN=0xb0000 +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="r9a06g032-rzn1-snarc" +CONFIG_SYS_LOAD_ADDR=0x80008000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8fffffff +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set +CONFIG_CMD_CLK=y +CONFIG_OF_CONTROL=y +CONFIG_RAM=y +CONFIG_CADENCE_DDR_CTRL=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/rzn1-snarc.h b/include/configs/rzn1-snarc.h new file mode 100644 index 0000000000..b97cb48eaa --- /dev/null +++ b/include/configs/rzn1-snarc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Schneider RZ/N1 board + */ + +#ifndef __RZN1_H +#define __RZN1_H + +/* Internal RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE (1 * 1024 * 1024) + +/* DDR */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE (256 * 1024 * 1024) + +#endif /* __RZN1_H */