From patchwork Wed Mar 8 20:26:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ralph Siemsen X-Patchwork-Id: 660466 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp523698wrb; Wed, 8 Mar 2023 12:29:10 -0800 (PST) X-Google-Smtp-Source: AK7set9M0J+2wTykiysZyqLFJ90/fTRluoAymJF/DfaRQrXyadTF3ur796PHRvzJQKySjVEpYNed X-Received: by 2002:a05:6808:f08:b0:37f:83a8:b858 with SMTP id m8-20020a0568080f0800b0037f83a8b858mr11009597oiw.3.1678307350633; Wed, 08 Mar 2023 12:29:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678307350; cv=none; d=google.com; s=arc-20160816; b=Ha7T7yUQaCZETDM4fY7GyvEoMkXknd9g8w3fvmzR53cGmDeFSMBJkotycO6fiXdwbc mzgnMCSh2qx0Cw4nMHgvojor9jKrpOR8X0Zo1r0FkRjGgazndlW+LIHk/+GO8s7+G3Pd 5T02yW4LXiMg70U8sVOjfLoUNszvdwrPxAmVSr78qPyREJspacO51TXtbsQUFoC4auJb UkuhooyKv9B/OsspqMnpJZ2gmM/YtYmK3ZJQvbNpfuRT5C0VuT3qIctoY2zw0JOtuojq wlq8XDEAACjm0mb/D5JvKjFHn18kv0cqLW0QCKHHABzsMs0sywxzbYhLHf/VIlqVobF4 NQgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CnPLzNQBlN+wHtKMaVCPVqAGqAE4J0yGTkeHE038Kl4=; b=birsbAdFkRnc0lFZILwaWhG7/9j+6T8xpmvuwVhucnQX7/eViwPTz4x6oPyaGhRe/y t6C4BJMa3ez1/tJP/iNhIjbtJSPXs7I7EPHRdW2kI0QDCMAeobfrMx9fMRAlZFkL0mKR RWMB+aioOJQyufIjimIHu7Ak04fiIB1PZWgQVW/teS2dmfI6G+mYd/Jkd9ipxsW2L4I3 SLucPh1gIKLNO0jpTVWx5OqPdansp2+MENhrmT5qUnNk4HY4XIEjHojv2ryyL0105ssx lTRLY4VphmXUICIl3ZEM58GRYBMYZlW/wvEsmLaBhAdJFLIcIUvaPkXM/N90Ni1onbdw lWTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTWrtmPM; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id j2-20020a544802000000b00383e1c09dbfsi15727196oij.142.2023.03.08.12.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:29:10 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTWrtmPM; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 04EC385EED; Wed, 8 Mar 2023 21:28:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="uTWrtmPM"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 83FBB85E88; Wed, 8 Mar 2023 21:27:32 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 38AE185EAF for ; Wed, 8 Mar 2023 21:27:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ralph.siemsen@linaro.org Received: by mail-qt1-x82e.google.com with SMTP id c18so19516815qte.5 for ; Wed, 08 Mar 2023 12:27:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678307230; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CnPLzNQBlN+wHtKMaVCPVqAGqAE4J0yGTkeHE038Kl4=; b=uTWrtmPMV6Xf8mtMr2bhUEuLu+taDmfgNUXrnOcYU/+Y/sKxtwCEtAfXlI/nQNg6HB sgwtq97OKXXq+dJ1VcYoG0HNfeiAULDOJx+qi2M0X1mfvRsGPGRpKp9bbU0kaAmD1BzO FAbMfEbxBMuY2ux7zNvhF6DUAanYhiOkwl//wD+qBlaNd+anXCaH6R7QFPFdDDMU2n1K Kh9/Dfpag+1eBjui4MPu9Hd7PQ23afBOQe6Qb/h4zexfyZgltdx/X7QhbhZkHQ2//8VG ebi28HBmssK1DdStbAKOvCs7dxeFPhvQW+RbAMgXBLYVw8a5wQHngN+zUnhCocTwtHV/ meig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678307230; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CnPLzNQBlN+wHtKMaVCPVqAGqAE4J0yGTkeHE038Kl4=; b=EQYH9erex+4WgZ1C2pyPOVbLfA76v3lu6Gx21QbYpBw9TPb9u4gTUy5rULYeIQ+6nC /apyQvrza2i7bl+GREhozCcjcIq2PY/GtU9gPAsepXNwXHlPKUnMasa87fLGffd2ygWj uB0xL/deQtT8ApkpzX60l7aiXn+z6FSdN9fr7vzaOFlkh649XNKoDjKFaLpg42Ait501 BrLXs990wtANfh1sd2Ieo1++RRL4e54KuC/bnPN0sanpnsKcjqjAHpJf0Kqj/xe1H2VT 5EBI8JlqVu4RZpavy3WpEa462zyVBiKPkGMa1wdigHU3jnVTGJHDG4BfHnkpLUhs2n6c Z6jw== X-Gm-Message-State: AO0yUKUhtvAVGSD2RfgYElb1iHgI64FVAMijzTEmxZE43UzQxhZuT6bG uqva4BGTF0/1jskhTreg4wDUt3POCrcEg6GZn4nLGQ== X-Received: by 2002:a05:622a:1a04:b0:3bf:c423:c36d with SMTP id f4-20020a05622a1a0400b003bfc423c36dmr37915382qtb.12.1678307230727; Wed, 08 Mar 2023 12:27:10 -0800 (PST) Received: from maple.netwinder.org (rfs.netwinder.org. [206.248.184.2]) by smtp.gmail.com with ESMTPSA id m2-20020ac84442000000b003b86b088755sm12144203qtn.15.2023.03.08.12.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:27:10 -0800 (PST) From: Ralph Siemsen To: u-boot@lists.denx.de Cc: Marek Vasut , Ralph Siemsen , Bharat Gooty , Rayagonda Kokatanur Subject: [PATCH v4 07/10] ARM: rzn1: basic support for Renesas RZ/N1 SoC Date: Wed, 8 Mar 2023 15:26:50 -0500 Message-Id: <20230308202653.1926303-8-ralph.siemsen@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308202653.1926303-1-ralph.siemsen@linaro.org> References: <20230308202653.1926303-1-ralph.siemsen@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RZ/N1 is a family of SoC devics from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support in the form of ARCH_RZN1 symbol. Signed-off-by: Ralph Siemsen --- (no changes since v1) arch/arm/Kconfig | 17 +++++++++++++++++ arch/arm/Makefile | 1 + arch/arm/mach-rzn1/Kconfig | 18 ++++++++++++++++++ arch/arm/mach-rzn1/Makefile | 3 +++ arch/arm/mach-rzn1/cpu_info.c | 19 +++++++++++++++++++ 5 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bd7fffcce0..8e2a30f852 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1031,6 +1031,21 @@ config ARCH_RMOBILE imply SYS_THUMB_BUILD imply ARCH_MISC_INIT if DISPLAY_CPUINFO +config ARCH_RZN1 + bool "Reneasa RZ/N1 SoC" + select CLK + select CLK_RENESAS + select CLK_R9A06G032 + select DM + select DM_ETH + select DM_SERIAL + select PINCTRL + select PINCONF + select REGMAP + select SYSRESET + select SYSRESET_SYSCON + imply CMD_DM + config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" select ARM64 @@ -2207,6 +2222,8 @@ source "arch/arm/mach-owl/Kconfig" source "arch/arm/mach-rmobile/Kconfig" +source "arch/arm/mach-rzn1/Kconfig" + source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-mediatek/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac602aed9c..1ec95a87e1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RMOBILE) += rmobile machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip +machine-$(CONFIG_ARCH_RZN1) += rzn1 machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon machine-$(CONFIG_ARCH_SOCFPGA) += socfpga diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig new file mode 100644 index 0000000000..707895874d --- /dev/null +++ b/arch/arm/mach-rzn1/Kconfig @@ -0,0 +1,18 @@ +if ARCH_RZN1 + +choice + prompt "Target Renesas RZ/N1 SoC select" + default RZN1 + +config RZN1 + bool "Renesas ARM SoCs RZ/N1 (32bit)" + select CPU_V7A + select ARMV7_SET_CORTEX_SMPEN if !SPL + select SPL_ARMV7_SET_CORTEX_SMPEN if SPL + +endchoice + +config SYS_SOC + default "rzn1" + +endif diff --git a/arch/arm/mach-rzn1/Makefile b/arch/arm/mach-rzn1/Makefile new file mode 100644 index 0000000000..b20f845c0f --- /dev/null +++ b/arch/arm/mach-rzn1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = cpu_info.o diff --git a/arch/arm/mach-rzn1/cpu_info.c b/arch/arm/mach-rzn1/cpu_info.c new file mode 100644 index 0000000000..37c2492b51 --- /dev/null +++ b/arch/arm/mach-rzn1/cpu_info.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + dcache_enable(); +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/N1\n"); + return 0; +} +#endif