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([223.178.212.120]) by smtp.gmail.com with ESMTPSA id x15-20020aa7956f000000b0058bacd6c4e8sm9797586pfq.207.2023.01.19.23.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 23:18:35 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH 14/14] dts: qcs404-evb: Add I2C controller nodes Date: Fri, 20 Jan 2023 12:47:19 +0530 Message-Id: <20230120071719.623661-15-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120071719.623661-1-sumit.garg@linaro.org> References: <20230120071719.623661-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/dts/qcs404-evb.dts | 97 +++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 2de0e7537b..8d7893c116 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -23,6 +23,11 @@ aliases { serial0 = &debug_uart; + i2c0 = &blsp1_i2c0; + i2c1 = &blsp1_i2c1; + i2c2 = &blsp1_i2c2; + i2c3 = &blsp1_i2c3; + i2c4 = &blsp1_i2c4; }; memory { @@ -49,6 +54,38 @@ function = "blsp_uart2"; }; + blsp1_i2c0_default: blsp1-i2c0-default { + pins = "GPIO_32", "GPIO_33"; + function = "blsp_i2c0"; + }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "GPIO_24", "GPIO_25"; + function = "blsp_i2c1"; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + sda { + pins = "GPIO_19"; + function = "blsp_i2c_sda_a2"; + }; + + scl { + pins = "GPIO_20"; + function = "blsp_i2c_scl_a2"; + }; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "GPIO_84", "GPIO_85"; + function = "blsp_i2c3"; + }; + + blsp1_i2c4_default: blsp1-i2c4-default { + pins = "GPIO_117", "GPIO_118"; + function = "blsp_i2c4"; + }; + ethernet_defaults: ethernet-defaults { int { pins = "GPIO_61"; @@ -105,6 +142,66 @@ }; }; + blsp1_i2c0: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + gcc: clock-controller@1800000 { compatible = "qcom,gcc-qcs404"; reg = <0x1800000 0x80000>;