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Thu, 14 Jan 2021 06:59:03 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH 01/13] imx: lowlevel: implement armv8_el2_to_aarch32 Date: Thu, 14 Jan 2021 15:27:58 +0800 Message-Id: <20210114072810.11873-1-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.28.0 X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR03CA0144.apcprd03.prod.outlook.com (2603:1096:4:c8::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR03CA0144.apcprd03.prod.outlook.com (2603:1096:4:c8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.6 via Frontend Transport; Thu, 14 Jan 2021 06:59:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8b7ccbec-20e5-4be4-9b2f-08d8b859e08e X-MS-TrafficTypeDiagnostic: DB7PR04MB4634: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:389; 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It will trap to ATF to let ATF handle the mode switching. Signed-off-by: Peng Fan --- arch/arm/mach-imx/lowlevel.S | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.28.0 diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S index 158fdb7d87..c500aa8123 100644 --- a/arch/arm/mach-imx/lowlevel.S +++ b/arch/arm/mach-imx/lowlevel.S @@ -20,3 +20,26 @@ ENTRY(lowlevel_init) isb ret ENDPROC(lowlevel_init) + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + ldr x0, =0xc20000fd + smc #0 + ret