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Mon, 28 Dec 2020 11:48:28 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH 01/13] imx: imx8mp_evk: enable eth support Date: Mon, 28 Dec 2020 20:16:58 +0800 Message-Id: <20201228121710.17235-1-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.28.0 X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR04CA0149.apcprd04.prod.outlook.com (2603:1096:3:16::33) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR04CA0149.apcprd04.prod.outlook.com (2603:1096:3:16::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3700.27 via Frontend Transport; Mon, 28 Dec 2020 11:48:26 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 183f79a2-9ddf-4fd7-574e-08d8ab267e41 X-MS-TrafficTypeDiagnostic: DB7PR04MB5993: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1091; 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SFP:1101; X-MS-Exchange-AntiSpam-MessageData: BgrEzjbFY2FTtyX+e9JR9RpNFcUaddvq+oRHbNim5j4/5Zjnh/UYkW/hdxhL3rHj28WAkkH9CNzsFnVzTq9KMGLiL6xy0AN7mManH74Hf+Y+juxC+dS7/xPCabUTQCWgkOcqI1LfHD24kAgNg0wKAidypAbXxr/n0opWZy5Yh9bRCyWKQzD7gGD+d3AiX6+sYtiNUHFmhw/GLCU0AhpTdCKK4wHjKkUZzQQSTL1co2pIjTe2FeXloBG0FE0KYVTbecc1NdqRtGZJH78sc2QpxfNkt0vKtK45WvSWLHHlV3gN9uf9a96SuOYv8S2wXjSOmMXM6d9lD9kzQEvjIO3oYbQBfUoPEH7CbC/GEX5YJ2UOMdPRVwb5SA8784jAE4MWaWXls38UcRcpNvCROqqkikLe5UYh+mL+J7cX7pxG29+xjT/0Negg8kxp9gIHa1wHb8USJgeKywjPoqqN1BSEFCjE48BxLTSXuR2V1hcf3TTRDZh735p+CED/QIJXvcmMbw9SBwoKzUoWYvnoh7jFh9MC2VLLs7EwCqpjuGmCJkc1BC/mZXAqnc6Nea2/6vMkfkNDFRPZcyHLA3rxpLn9Od4YwZLewueuPP6f7Wjhjiskd2UD8M2Cx0ktxf3AMj9glrC8TqoebyQuk+xXddXGhJV7wUz7QqBFmuK5EeoB5WVEN6ocdsV4xSjQBK7k0QlTtHaA5Zj+oH79+dp7WPdEMA1S/Z0iazOHW2rALEcfZEx4UubsOQ2/PGOeUDyaDfe1A2UTnayeVkdJe71nrb7dyRWS7UmCQJbnqLrORedBbk/7FYayqBXF8HnHEIWqXFQWjk4S6ywISTuW0FZINMZUIQyYiKe0lH/AdJAD8kI7XscYHsqTSQl9m3VBEVgARi1TD8OF6CeACxwuA+qnttXknRot8eHvzelqz6K+NHvZDdaSpqnKuIhUiIegclVBxiJKt3qTy/cQo40fg5L9HmA+sxmIuzkhww57gu2IjcaNFy74XNAJpLPIJQ23lQM1UUmv X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-AuthSource: DB6PR0402MB2760.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Dec 2020 11:48:28.7593 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: 183f79a2-9ddf-4fd7-574e-08d8ab267e41 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wunk84mTSppwhGSR3jbDDBca+iMKZUo1SoO77+n4EECoI80TKPObjdjpiPgHsW2APaQkMpaMpjjkJkRiCOf+ng== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB5993 X-Mailman-Approved-At: Mon, 28 Dec 2020 14:26:27 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Peng Fan Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 + board/freescale/imx8mp_evk/imx8mp_evk.c | 81 ++++++++++++++++++++++ configs/imx8mp_evk_defconfig | 11 +++ include/configs/imx8mp_evk.h | 16 +++++ 4 files changed, 110 insertions(+) -- 2.28.0 diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index f1c410ec78..f5711155b7 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -62,6 +62,8 @@ #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 + #if !defined(__ASSEMBLY__) #include #include diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 034a349236..d6b863df84 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -7,9 +7,13 @@ #include #include #include +#include +#include +#include #include #include #include +#include #include #include @@ -40,8 +44,85 @@ int board_early_init_f(void) return 0; } +#define FEC_RST_PAD IMX_GPIO_NR(4, 2) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + mdelay(15); + gpio_direction_output(FEC_RST_PAD, 1); + mdelay(100); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); + + return 0; +} + +#define EQOS_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const eqos_rst_pads[] = { + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_eqos(void) +{ + imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, + ARRAY_SIZE(eqos_rst_pads)); + + gpio_request(EQOS_RST_PAD, "eqos_rst"); + gpio_direction_output(EQOS_RST_PAD, 0); + mdelay(15); + gpio_direction_output(EQOS_RST_PAD, 1); + mdelay(100); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_eqos(); + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + int board_init(void) { + if (CONFIG_IS_ENABLED(FEC_MXC)) + setup_fec(); + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + setup_eqos(); + return 0; } diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index cd5724e811..de9db697e8 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -73,6 +73,14 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y + +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y + CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -85,3 +93,6 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_WATCHDOG=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 8253c6aa2f..7abaf5ff84 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -44,6 +44,22 @@ #endif +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 +#define FEC_QUIRK_ENET_MAC + +#define DWC_NET_PHYADDR 1 +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \