| Message ID | 20200916071722.28772-4-peng.fan@nxp.com |
|---|---|
| State | New |
| Headers | show
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Wed, 16 Sep 2020 06:53:15 +0000 From: peng.fan@nxp.com To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan <peng.fan@nxp.com> Subject: [PATCH 4/5] imx8m: clock_imx8mm: add missed return Date: Wed, 16 Sep 2020 15:17:21 +0800 Message-Id: <20200916071722.28772-4-peng.fan@nxp.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200916071722.28772-1-peng.fan@nxp.com> References: <20200916071722.28772-1-peng.fan@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR06CA0230.apcprd06.prod.outlook.com (2603:1096:4:ac::14) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0230.apcprd06.prod.outlook.com (2603:1096:4:ac::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3391.11 via Frontend Transport; Wed, 16 Sep 2020 06:53:12 +0000 X-Mailer: git-send-email 2.28.0 X-Originating-IP: [119.31.174.71] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 81194f96-2cbc-4a81-d16d-08d85a0d2f4b X-MS-TrafficTypeDiagnostic: DB7PR04MB4762: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: <DB7PR04MB4762F8E897516A5B1CCD255288210@DB7PR04MB4762.eurprd04.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:296; 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[1/5] imx7: ccm: correct target interface num
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diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 3610f5b2fc..9dde11cded 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -360,6 +360,7 @@ void init_clk_ecspi(u32 index) clock_enable(CCGR_ECSPI2, 0); clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); clock_enable(CCGR_ECSPI2, 1); + return; case 2: clock_enable(CCGR_ECSPI3, 0); clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));