From patchwork Fri Jul 10 12:55:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 241310 List-Id: U-Boot discussion From: chee.hong.ang at intel.com (Chee Hong Ang) Date: Fri, 10 Jul 2020 20:55:20 +0800 Subject: [PATCH v1 1/4] clk: agilex: Add NAND clock support In-Reply-To: <20200710125523.68008-1-chee.hong.ang@intel.com> References: <20200710125523.68008-1-chee.hong.ang@intel.com> Message-ID: <20200710125523.68008-2-chee.hong.ang@intel.com> From: Ley Foon Tan Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- drivers/clk/altera/clk-agilex.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 0042958f4c..2ef9292f93 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -533,7 +533,10 @@ static ulong socfpga_clk_get_rate(struct clk *clk) case AGILEX_EMAC2_CLK: return clk_get_emac_clk_hz(plat, clk->id); case AGILEX_USB_CLK: + case AGILEX_NAND_X_CLK: return clk_get_l4_mp_clk_hz(plat); + case AGILEX_NAND_CLK: + return clk_get_l4_mp_clk_hz(plat) / 4; default: return -ENXIO; }