From patchwork Tue Jun 30 10:33:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 243126 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Tue, 30 Jun 2020 12:33:19 +0200 Subject: [PATCH v2 4/5] mips: cache: Make invalidate_dcache_range() weak to enable overwrite In-Reply-To: <20200630103320.1290545-1-sr@denx.de> References: <20200630103320.1290545-1-sr@denx.de> Message-ID: <20200630103320.1290545-5-sr@denx.de> This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, which will be done for Octeon. Signed-off-by: Stefan Roese --- (no changes since v1) arch/mips/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index ad37f05802..cf29994a7a 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -159,7 +159,7 @@ void __weak flush_dcache_range(ulong start_addr, ulong stop) sync(); } -void invalidate_dcache_range(ulong start_addr, ulong stop) +void __weak invalidate_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); unsigned long slsize = scache_line_size();