From patchwork Wed Jun 10 10:41:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rayagonda Kokatanur X-Patchwork-Id: 242056 List-Id: U-Boot discussion From: rayagonda.kokatanur at broadcom.com (Rayagonda Kokatanur) Date: Wed, 10 Jun 2020 16:11:15 +0530 Subject: [PATCH v3 10/15] dt-bindings: memory: ns3: add ddr memory definition In-Reply-To: <20200610104120.30668-1-rayagonda.kokatanur@broadcom.com> References: <20200610104120.30668-1-rayagonda.kokatanur@broadcom.com> Message-ID: <20200610104120.30668-11-rayagonda.kokatanur@broadcom.com> Add ddr memory definitions. Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- include/dt-bindings/memory/bcm-ns3-mc.h | 30 ++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index d6e7717ba2..d04b842d19 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -7,7 +7,8 @@ #define DT_BINDINGS_BCM_NS3_MC_H /* - * Reserved Memory Map : SHMEM & TZDRAM. + * +--------+----------+ 0x8B000000 + * | NITRO CRASH DUMP | 32MB * +--------+----------+ 0x8D000000 * | SHMEM (NS) | 16 MB * +-------------------+ 0x8E000000 @@ -20,6 +21,10 @@ * +-------------------+ 0x8F100000 */ +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8AE00000 +#define BCM_NS3_MEM_NITRO_CRASH_LEN 0x21fffff +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x2200000 + #define BCM_NS3_MEM_SHARE_START 0x8D000000 #define BCM_NS3_MEM_SHARE_LEN 0x020FFFFF @@ -31,7 +36,30 @@ #define BCM_NS3_MEM_CRMU_PT_START 0x880000000 #define BCM_NS3_MEM_CRMU_PT_LEN 0x200000 +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x80000000UL +#define BCM_NS3_MEM_LEN 0x80000000UL +#define BCM_NS3_MEM_END (BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x880000000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x180000000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8F220000 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + #define BCM_NS3_GIC_LPI_BASE 0x8AD70000 #define BCM_NS3_GIC_LPI_SIZE 0x90000 +#define BCM_NS3_MEM_RSVE_START BCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START 0x880000000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x100000 #endif