From patchwork Fri Jun 5 12:44:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 241827 List-Id: U-Boot discussion From: p.yadav at ti.com (Pratyush Yadav) Date: Fri, 5 Jun 2020 18:14:55 +0530 Subject: [PATCH v6 16/21] mtd: spi-nor-core: Do not make invalid quad enable fatal In-Reply-To: <20200605124500.17867-1-p.yadav@ti.com> References: <20200605124500.17867-1-p.yadav@ti.com> Message-ID: <20200605124500.17867-17-p.yadav@ti.com> The Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved"). While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 95743c3fb6..13a112b6a6 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2093,7 +2093,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; #endif default: - return -EINVAL; + dev_dbg(nor->dev, "BFPT QER reserved value used\n"); + break; } /* Stop here if JESD216 rev B. */