From patchwork Mon Jun 1 19:53:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 241473 List-Id: U-Boot discussion From: michael at walle.cc (Michael Walle) Date: Mon, 1 Jun 2020 21:53:29 +0200 Subject: [PATCH v2 06/13] armv8: layerscape: fix alignment for spin table In-Reply-To: <20200601195336.3237-1-michael@walle.cc> References: <20200601195336.3237-1-michael@walle.cc> Message-ID: <20200601195336.3237-7-michael@walle.cc> Fix the alignment so it will match the comments. The spin table has to be 8 byte aligned, so ".align 3" is enough. Signed-off-by: Michael Walle --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index ac9c622aee..a92f930e04 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -19,7 +19,7 @@ secondary_boot_addr: .ltorg /* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 + .align 3 .global secondary_boot_code /* Secondary Boot Code starts here */ secondary_boot_code: @@ -144,7 +144,7 @@ ENDPROC(secondary_switch_to_el1) .ltorg /* 64 bit alignment for elements accessed as data */ - .align 4 + .align 3 .global __real_cntfrq __real_cntfrq: .quad COUNTER_FREQUENCY