From patchwork Sat May 30 08:10:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 246866 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Sat, 30 May 2020 16:10:06 +0800 Subject: [PATCH V2 1/7] driver: ddr: imx: skip ddr_ss_gpr config on imx8mn In-Reply-To: <20200530081012.26573-1-peng.fan@nxp.com> References: <20200530081012.26573-1-peng.fan@nxp.com> Message-ID: <20200530081012.26573-2-peng.fan@nxp.com> From: Jacky Bai There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting this register on i.MX8MN. Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/ddr_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index af8c1427d2..ba5ae05035 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -73,7 +73,7 @@ int ddr_init(struct dram_timing_info *dram_timing) /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5)) + if (tmp & (0x1 << 5) && !is_imx8mn()) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */