diff mbox series

[v13,03/19] riscv: Add _image_binary_end for SPL

Message ID	20200529060340.26708-4-pragnesh.patel@sifive.com
State	Accepted
Commit	bbb94af981ad63c0dd9ab86e25c195c3cbc9a0e6
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Fri, 29 May 2020 11:33:23 +0530 Subject: [PATCH v13 03/19] riscv: Add _image_binary_end for SPL In-Reply-To: <20200529060340.26708-1-pragnesh.patel@sifive.com> References: <20200529060340.26708-1-pragnesh.patel@sifive.com> Message-ID: <20200529060340.26708-4-pragnesh.patel@sifive.com>
Series	RISC-V SiFive FU540 support SPL \| expand [v13,00/19] RISC-V SiFive FU540 support SPL [v13,01/19] misc: add driver for the SiFive otp controller [v13,02/19] riscv: sifive: fu540: Use OTP DM driver for serial environment variable [v13,03/19] riscv: Add _image_binary_end for SPL [v13,04/19] lib: Makefile: build crc7.c when CONFIG_MMC_SPI [v13,05/19] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files [v13,06/19] sifive: fu540: add ddr driver [v13,07/19] sifive: dts: fu540: Add DDR controller and phy register settings [v13,08/19] riscv: sifive: dts: fu540: add U-Boot dmc node [v13,09/19] clk: sifive: fu540-prci: Add clock enable and disable ops [v13,10/19] clk: sifive: fu540-prci: Add ddr clock initialization [v13,11/19] clk: sifive: fu540-prci: Release ethernet clock reset [v13,12/19] riscv: sifive: dts: fu540: set ethernet clock rate [v13,13/19] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux [v13,14/19] riscv: cpu: fu540: Add support for cpu fu540 [v13,15/19] riscv: sifive: fu540: add SPL configuration [v13,16/19] sifive: fu540: Add sample SD gpt partition layout [v13,17/19] sifive: fu540: Add U-Boot proper sector start [v13,18/19] configs: fu540: Add config options for U-Boot SPL [v13,19/19] doc: sifive: fu540: Add description for OpenSBI generic platform

Commit Message

Pragnesh Patel May 29, 2020, 6:03 a.m. UTC

For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
Reviewed-by: Anup Patel <anup.patel at wdc.com>
Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Jagan Teki <jagan at amarulasolutions.com>
---
 arch/riscv/cpu/u-boot-spl.lds | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@  SECTIONS
 	. = ALIGN(4);
 
 	_end = .;
+	_image_binary_end = .;
 
 	.bss : {
 		__bss_start = .;