From patchwork Fri May 29 06:03:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pragnesh Patel X-Patchwork-Id: 246797 List-Id: U-Boot discussion From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Fri, 29 May 2020 11:33:32 +0530 Subject: [PATCH v13 12/19] riscv: sifive: dts: fu540: set ethernet clock rate In-Reply-To: <20200529060340.26708-1-pragnesh.patel@sifive.com> References: <20200529060340.26708-1-pragnesh.patel@sifive.com> Message-ID: <20200529060340.26708-13-pragnesh.patel@sifive.com> Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel Tested-by: Bin Meng --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index fc91a7c987..9bba554f9d 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -82,3 +82,8 @@ &qspi2 { u-boot,dm-spl; }; + +ð0 { + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clock-rates = <125000000>; +};