| Message ID | 20200529060340.26708-13-pragnesh.patel@sifive.com |
|---|---|
| State | Accepted |
| Commit | 329e023868f28fd2cda31dc788017ef7c48fb1a8 |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Fri, May 29, 2020 at 2:05 PM Pragnesh Patel <pragnesh.patel at sifive.com> wrote: > > Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, > Earlier this is done by FSBL. With this change We can remove the > ethernet clock rate code from FSBL. > > Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> > --- > arch/riscv/dts/fu540-c000-u-boot.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > Tested-by: Bin Meng <bmeng.cn at gmail.com>
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index fc91a7c987..9bba554f9d 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -82,3 +82,8 @@ &qspi2 { u-boot,dm-spl; }; + +ð0 { + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clock-rates = <125000000>; +};
Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+)