From patchwork Wed May 27 16:46:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 246741 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 27 May 2020 22:16:38 +0530 Subject: [PATCH 07/24] arm: Remove configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig board In-Reply-To: <20200527164655.177741-1-jagan@amarulasolutions.com> References: <20200527164655.177741-1-jagan@amarulasolutions.com> Message-ID: <20200527164655.177741-8-jagan@amarulasolutions.com> This board has not been converted to CONFIG_DM_SPI by the deadline. Remove it. Patch-cc: Qiang Zhao Signed-off-by: Jagan Teki Nacked-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 1 - board/freescale/p1010rdb/Kconfig | 14 - board/freescale/p1010rdb/MAINTAINERS | 33 - board/freescale/p1010rdb/Makefile | 24 - board/freescale/p1010rdb/README.P1010RDB-PA | 208 ----- board/freescale/p1010rdb/README.P1010RDB-PB | 188 ----- board/freescale/p1010rdb/ddr.c | 235 ------ board/freescale/p1010rdb/law.c | 16 - board/freescale/p1010rdb/p1010rdb.c | 731 ----------------- board/freescale/p1010rdb/spl.c | 114 --- board/freescale/p1010rdb/spl_minimal.c | 65 -- board/freescale/p1010rdb/tlb.c | 90 -- .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 63 -- configs/P1010RDB-PA_36BIT_NAND_defconfig | 85 -- .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 62 -- configs/P1010RDB-PA_36BIT_NOR_defconfig | 67 -- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 79 -- ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 64 -- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 81 -- configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 62 -- configs/P1010RDB-PA_NAND_defconfig | 84 -- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 60 -- configs/P1010RDB-PA_NOR_defconfig | 66 -- configs/P1010RDB-PA_SDCARD_defconfig | 78 -- .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 63 -- configs/P1010RDB-PA_SPIFLASH_defconfig | 80 -- .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 63 -- configs/P1010RDB-PB_36BIT_NAND_defconfig | 85 -- .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 62 -- configs/P1010RDB-PB_36BIT_NOR_defconfig | 67 -- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 79 -- ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 64 -- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 81 -- configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 62 -- configs/P1010RDB-PB_NAND_defconfig | 84 -- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 61 -- configs/P1010RDB-PB_NOR_defconfig | 66 -- configs/P1010RDB-PB_SDCARD_defconfig | 78 -- .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 63 -- configs/P1010RDB-PB_SPIFLASH_defconfig | 80 -- include/configs/P1010RDB.h | 766 ------------------ 41 files changed, 4474 deletions(-) delete mode 100644 board/freescale/p1010rdb/Kconfig delete mode 100644 board/freescale/p1010rdb/MAINTAINERS delete mode 100644 board/freescale/p1010rdb/Makefile delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PA delete mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB delete mode 100644 board/freescale/p1010rdb/ddr.c delete mode 100644 board/freescale/p1010rdb/law.c delete mode 100644 board/freescale/p1010rdb/p1010rdb.c delete mode 100644 board/freescale/p1010rdb/spl.c delete mode 100644 board/freescale/p1010rdb/spl_minimal.c delete mode 100644 board/freescale/p1010rdb/tlb.c delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_SDCARD_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_NAND_defconfig delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_NOR_defconfig delete mode 100644 configs/P1010RDB-PA_SDCARD_defconfig delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_SPIFLASH_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_SDCARD_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_NAND_defconfig delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_NOR_defconfig delete mode 100644 configs/P1010RDB-PB_SDCARD_defconfig delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_SPIFLASH_defconfig delete mode 100644 include/configs/P1010RDB.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 1842d71f24..ece589ba90 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1597,7 +1597,6 @@ source "board/freescale/mpc8555cds/Kconfig" source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" -source "board/freescale/p1010rdb/Kconfig" source "board/freescale/p1022ds/Kconfig" source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig deleted file mode 100644 index 3adac4af1e..0000000000 --- a/board/freescale/p1010rdb/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB - -config SYS_BOARD - default "p1010rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P1010RDB" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS deleted file mode 100644 index c9f7fa3e2a..0000000000 --- a/board/freescale/p1010rdb/MAINTAINERS +++ /dev/null @@ -1,33 +0,0 @@ -P1010RDB BOARD -M: Qiang Zhao -S: Maintained -F: board/freescale/p1010rdb/ -F: include/configs/P1010RDB.h -F: configs/P1010RDB-PA_36BIT_NAND_defconfig -F: configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig -F: configs/P1010RDB-PA_36BIT_NOR_defconfig -F: configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig -F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig -F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig -F: configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig -F: configs/P1010RDB-PA_NAND_defconfig -F: configs/P1010RDB-PA_NAND_SECBOOT_defconfig -F: configs/P1010RDB-PA_NOR_defconfig -F: configs/P1010RDB-PA_NOR_SECBOOT_defconfig -F: configs/P1010RDB-PA_SDCARD_defconfig -F: configs/P1010RDB-PA_SPIFLASH_defconfig -F: configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig -F: configs/P1010RDB-PB_36BIT_NAND_defconfig -F: configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig -F: configs/P1010RDB-PB_36BIT_NOR_defconfig -F: configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig -F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig -F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig -F: configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig -F: configs/P1010RDB-PB_NAND_defconfig -F: configs/P1010RDB-PB_NAND_SECBOOT_defconfig -F: configs/P1010RDB-PB_NOR_defconfig -F: configs/P1010RDB-PB_NOR_SECBOOT_defconfig -F: configs/P1010RDB-PB_SDCARD_defconfig -F: configs/P1010RDB-PB_SPIFLASH_defconfig -F: configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile deleted file mode 100644 index 36b34c70aa..0000000000 --- a/board/freescale/p1010rdb/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif -obj-y += p1010rdb.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA deleted file mode 100644 index 105942f7a5..0000000000 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ /dev/null @@ -1,208 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5? 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn U-Boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff40000 +$filesize - => erase eff40000 +$filesize - => cp.b $loadaddr eff40000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef40000 +$filesize - => erase eef40000 +$filesize - => cp.b $loadaddr eef40000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn U-Boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn U-Boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB User Guide and access website -www.freescale.com diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB deleted file mode 100644 index dc82f0df09..0000000000 --- a/board/freescale/p1010rdb/README.P1010RDB-PB +++ /dev/null @@ -1,188 +0,0 @@ -Overview -========= -The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. -P1010RDB-PB is a variation of previous P1010RDB-PA board. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that -addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB-PB board features are as following: -Memory subsystem: - - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32M bytes NOR flash single-chip memory - - 2G bytes NAND flash memory - - 16M bytes SPI memory - - 256K bit M24256 I2C EEPROM - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) - - PCIe 2.0: two x1 mini-PCIe slots - - SATA 2.0: two SATA interfaces - - USB 2.0: one USB interface - - FlexCAN: two FlexCAN interfaces (revision 2.0B) - - UART: one USB-to-Serial interface - - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. - 1 FXO port connected via a relay to FXS for switchover to POTS - -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging - -POR: support critical POR setting changed via switch on board -PCB: 6-layer routing (4-layer signals, 2-layer power and ground) - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -P1010RDB-PB default DIP-switch settings -======================================= -SW1[1:8]= 10101010 -SW2[1:8]= 11011000 -SW3[1:8]= 10010000 -SW4[1:4]= 1010 -SW5[1:8]= 11111010 - - -P1010RDB-PB boot mode settings via DIP-switch -============================================= -SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot -SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot -SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot -SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot -Note: 1 stands for 'on', 0 stands for 'off' - - -Switch P1010RDB-PB boot mode via software without setting DIP-switch -==================================================================== -=> run boot_bank0 (boot from NOR bank0) -=> run boot_bank1 (boot from NOR bank1) -=> run boot_nand (boot from NAND flash) -=> run boot_spi (boot from SPI flash) -=> run boot_sd (boot from SD card) - - -Frequency combination support on P1010RDB-PB -============================================= -SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) -0101 1 1010 0 800 400 800 -1001 1 1010 0 800 400 667 -1010 1 1100 0 667 333 667 -1000 0 1010 0 533 266 667 -0101 1 1010 1 1000 400 800 -1001 1 1010 1 1000 400 667 - - -Setting of pin mux -================== -Since pins multiplexing, TDM and CAN are muxed with SPI flash. -SDHC is muxed with IFC. IFC and SPI flash are enabled by default. - -To enable TDM: -=> setenv hwconfig fsl_p1010mux:tdm_can=tdm -=> save;reset - -To enable FlexCAN: -=> setenv hwconfig fsl_p1010mux:tdm_can=can -=> save;reset - -To enable SDHC in case of NOR/NAND/SPI boot - a) For temporary use case in runtime without reboot system - run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC. - - b) For long-term use case - set 'esdhc' in hwconfig and save it. - -To enable IFC in case of SD boot - a) For temporary use case in runtime without reboot system - run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC. - - b) For long-term use case - set 'ifc' in hwconfig and save it. - - -Build images for different boot mode -==================================== -First setup cross compile environment on build host - $ export ARCH=powerpc - $ export CROSS_COMPILE=/powerpc-linux-gnu- - -1. For NOR boot - $ make P1010RDB-PB_NOR - -2. For NAND boot - $ make P1010RDB-PB_NAND - -3. For SPI boot - $ make P1010RDB-PB_SPIFLASH - -4. For SD boot - $ make P1010RDB-PB_SDCARD - - -Steps to program images to flash for different boot mode -======================================================== -1. NOR boot - => tftp 1000000 u-boot.bin - For bank0 - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - - For bank1 - => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize - set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - -2. NAND boot - => tftp 1000000 u-boot-nand.bin - => nand erase 0 $filesize; nand write $loadaddr 0 $filesize - Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board - -3. SPI boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin - 2) => tftp 1000000 u-boot-spi-combined.bin - 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 - set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board - -4. SD boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin - 2) => tftp 1000000 u-boot-sd-combined.bin - 3) => mux sdhc - 4) => mmc write 1000000 0 1050 - set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board - - -Boot Linux from network using TFTP on P1010RDB-PB -================================================= -Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB-PB User Guide and access website -www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c deleted file mode 100644 index 71f6259b60..0000000000 --- a/board/freescale/p1010rdb/ddr.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_DRAM_SIZE 1024 - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {607, 749, &ddr_cfg_regs_667}, - {0, 0, NULL} -}; - -unsigned long get_sdram_size(void) -{ - struct cpu_type *cpu; - phys_size_t ddr_size; - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014) - ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); - else - ddr_size = CONFIG_SYS_DRAM_SIZE; - - return ddr_size; -} - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - struct cpu_type *cpu; - -#if defined(CONFIG_SYS_RAMBOOT) - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -#endif - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16bit DDR width */ - if (cpu->soc_ver == SVR_P1014) { - ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; - ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - /* divide SA and EA by two and then mask the rest so we don't - * write to reserved fields */ - ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; - } - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, - LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - - return ddr_size; -} - -#else /* CONFIG_SYS_DDR_RAW_TIMING */ -/* - * Samsung K4B2G0846C-HCF8 - * The following timing are for "downshift" - * i.e. to use CL9 part as CL7 - * otherwise, tAA, tRCD, tRP will be 13500ps - * and tRC will be 49500ps - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1875, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct cpu_type *cpu; - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014) - popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c deleted file mode 100644 index debf571482..0000000000 --- a/board/freescale/p1010rdb/law.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c deleted file mode 100644 index 66ccc0bd1e..0000000000 --- a/board/freescale/p1010rdb/p1010rdb.c +++ /dev/null @@ -1,731 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define GPIO4_PCIE_RESET_SET 0x08000000 -#define MUX_CPLD_CAN_UART 0x00 -#define MUX_CPLD_TDM 0x01 -#define MUX_CPLD_SPICS0_FLASH 0x00 -#define MUX_CPLD_SPICS0_SLIC 0x02 -#define PMUXCR1_IFC_MASK 0x00ffff00 -#define PMUXCR1_SDHC_MASK 0x00fff000 -#define PMUXCR1_SDHC_ENABLE 0x00555000 - -enum { - MUX_TYPE_IFC, - MUX_TYPE_SDHC, - MUX_TYPE_SPIFLASH, - MUX_TYPE_TDM, - MUX_TYPE_CAN, - MUX_TYPE_CS0_NOR, - MUX_TYPE_CS0_NAND, -}; - -enum { - I2C_READ_BANK, - I2C_READ_PCB_VER, -}; - -static uint sd_ifc_mux; - -struct cpld_data { - u8 cpld_ver; /* cpld revision */ -#if defined(CONFIG_TARGET_P1010RDB_PA) - u8 pcba_ver; /* pcb revision number */ - u8 twindie_ddr3; - u8 res1[6]; - u8 bank_sel; /* NOR Flash bank */ - u8 res2[5]; - u8 usb2_sel; - u8 res3[1]; - u8 porsw_sel; - u8 tdm_can_sel; - u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ - u8 por0; /* POR Options */ - u8 por1; /* POR Options */ - u8 por2; /* POR Options */ - u8 por3; /* POR Options */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) - u8 rom_loc; -#endif -}; - -int board_early_init_f(void) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - /* - * Reset PCIe slots via GPIO4 - */ - setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); - setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - - set_tlb(1, flashbase + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); - return 0; -} - -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - -int config_board_mux(int ctrl_type) -{ - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u8 tmp; - -#ifdef CONFIG_DM_I2C - struct udevice *dev; - int ret; -#if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, - I2C_PCA9557_ADDR1, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, I2C_PCA9557_BUS_NUM); - return ret; - } - switch (ctrl_type) { - case MUX_TYPE_IFC: - tmp = 0xf0; - dm_i2c_write(dev, 3, &tmp, 1); - tmp = 0x01; - dm_i2c_write(dev, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - tmp = 0xf0; - dm_i2c_write(dev, 3, &tmp, 1); - tmp = 0x05; - dm_i2c_write(dev, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); - break; - case MUX_TYPE_TDM: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - break; - case MUX_TYPE_CAN: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - break; - default: - break; - } -#elif defined(CONFIG_TARGET_P1010RDB_PB) - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, - I2C_PCA9557_ADDR2, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, I2C_PCA9557_BUS_NUM); - return ret; - } - switch (ctrl_type) { - case MUX_TYPE_IFC: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 3, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x04); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 3, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x80); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x80); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_TDM: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x82); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x82); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CAN: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x02); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x02); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CS0_NOR: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CS0_NAND: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x08); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 3, &tmp, 1); - break; - default: - break; - } -#endif -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x01; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x05; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); - break; - case MUX_TYPE_TDM: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - break; - case MUX_TYPE_CAN: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - break; - default: - break; - } -#elif defined(CONFIG_TARGET_P1010RDB_PB) - uint orig_bus = i2c_get_bus_num(); - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_TDM: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CAN: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NOR: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NAND: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - default: - break; - } - i2c_set_bus_num(orig_bus); -#endif -#endif - return 0; -} - -#ifdef CONFIG_TARGET_P1010RDB_PB -int i2c_pca9557_read(int type) -{ - u8 val; - int bus_num = I2C_PCA9557_BUS_NUM; - -#ifdef CONFIG_DM_I2C - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, bus_num); - return ret; - } - dm_i2c_read(dev, 0, &val, 1); -#else - i2c_set_bus_num(bus_num); - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); -#endif - - switch (type) { - case I2C_READ_BANK: - val = (val & 0x10) >> 4; - break; - case I2C_READ_PCB_VER: - val = ((val & 0x60) >> 5) + 1; - break; - default: - break; - } - - return val; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - u8 val; - - cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P1010RDB_PA) - printf("Board: %sRDB-PA, ", cpu->name); -#elif defined(CONFIG_TARGET_P1010RDB_PB) - printf("Board: %sRDB-PB, ", cpu->name); -#ifdef CONFIG_DM_I2C - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - I2C_PCA9557_BUS_NUM); - return ret; - } - val = 0x0; /* no polarity inversion */ - dm_i2c_write(dev, 2, &val, 1); -#else - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); - val = 0x0; /* no polarity inversion */ - i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); -#endif -#endif - -#ifdef CONFIG_SDCARD - /* switch to IFC to read info from CPLD */ - config_board_mux(MUX_TYPE_IFC); -#endif - -#if defined(CONFIG_TARGET_P1010RDB_PA) - val = (in_8(&cpld_data->pcba_ver) & 0xf); - printf("PCB: v%x.0\n", val); -#elif defined(CONFIG_TARGET_P1010RDB_PB) - val = in_8(&cpld_data->cpld_ver); - printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); - printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); - val = in_8(&cpld_data->rom_loc) & 0xf; - puts("Boot from: "); - switch (val) { - case 0xf: - config_board_mux(MUX_TYPE_CS0_NOR); - printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); - break; - case 0xe: - puts("SDHC\n"); - val = 0x60; /* set pca9557 pin input/output */ -#ifdef CONFIG_DM_I2C - dm_i2c_write(dev, 3, &val, 1); -#else - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); -#endif - break; - case 0x5: - config_board_mux(MUX_TYPE_IFC); - config_board_mux(MUX_TYPE_CS0_NAND); - puts("NAND\n"); - break; - case 0x6: - config_board_mux(MUX_TYPE_IFC); - puts("SPI\n"); - break; - default: - puts("unknown\n"); - break; - } -#endif - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - struct cpu_type *cpu; - int num = 0; - - cpu = gd->arch.cpu; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; - } -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_del_flexcan(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,p1010-flexcan")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_flash(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "spansion,s25sl12801")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_slic(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "zarlink,le88266")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_tdm(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,starlite-tdm")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_sdhc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,esdhc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_ifc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,ifc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_disable_uart1(void *blob) -{ - int nodeoff; - - nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CONFIG_SYS_NS16550_COM2); - - if (nodeoff > 0) { - fdt_status_disabled(blob, nodeoff); - } else { - printf("WARNING unable to set status for fsl,ns16550 " - "uart1: %s\n", fdt_strerror(nodeoff)); - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - struct cpu_type *cpu; - - cpu = gd->arch.cpu; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) - FT_FSL_PCI_SETUP; -#endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - - /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014) { - fdt_del_flexcan(blob); - fdt_del_node_and_alias(blob, "ethernet2"); - } - - /* Delete IFC node as IFC pins are multiplexing with SDHC */ - if (sd_ifc_mux != MUX_TYPE_IFC) - fdt_del_ifc(blob); - else - fdt_del_sdhc(blob); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - fdt_del_tdm(blob); - fdt_del_spi_slic(blob); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - fdt_del_flexcan(blob); - fdt_del_spi_flash(blob); - fdt_disable_uart1(blob); - } else { - /* - * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" - * explicitly, defaultly spi_cs_sel to spi-flash instead of - * to tdm/slic. - */ - fdt_del_tdm(blob); - fdt_del_flexcan(blob); - fdt_disable_uart1(blob); - } - - return 0; -} -#endif - -#ifdef CONFIG_SDCARD -int board_mmc_init(bd_t *bis) -{ - config_board_mux(MUX_TYPE_SDHC); - return -1; -} -#else -void board_reset(void) -{ - /* mux to IFC to enable CPLD for reset */ - if (sd_ifc_mux != MUX_TYPE_IFC) - config_board_mux(MUX_TYPE_IFC); -} -#endif - - -int misc_init_r(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | - MPC85xx_PMUXCR_CAN1_UART | - MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN2_UART); - config_board_mux(MUX_TYPE_CAN); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | - MPC85xx_PMUXCR_CAN1_UART); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN1_TDM); - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - config_board_mux(MUX_TYPE_TDM); - } else { - /* defaultly spi_cs_sel to flash */ - config_board_mux(MUX_TYPE_SPIFLASH); - } - - if (hwconfig("esdhc")) - config_board_mux(MUX_TYPE_SDHC); - else if (hwconfig("ifc")) - config_board_mux(MUX_TYPE_IFC); - -#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - return 0; -} - -#ifndef CONFIG_SPL_BUILD -static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc < 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "ifc") == 0) - config_board_mux(MUX_TYPE_IFC); - else if (strcmp(argv[1], "sdhc") == 0) - config_board_mux(MUX_TYPE_SDHC); - else - return CMD_RET_USAGE; - return 0; -} - -U_BOOT_CMD( - mux, 2, 0, pin_mux_cmd, - "configure multiplexing pin for IFC/SDHC bus in runtime", - "bus_type (e.g. mux sdhc)" -); -#endif diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c deleted file mode 100644 index 159d14b024..0000000000 --- a/board/freescale/p1010rdb/spl.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - - console_init_f(); - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - -#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - bd_t *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif - - i2c_init_all(); - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("\nTertiary program loader running in sram..."); -#else - puts("\nSecond program loader running in sram..."); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c deleted file mode 100644 index 0bb2c83872..0000000000 --- a/board/freescale/p1010rdb/spl_minimal.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c deleted file mode 100644 index 04faefe994..0000000000 --- a/board/freescale/p1010rdb/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 3, BOOKE_PAGESZ_16M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -#endif -#endif - - /* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig deleted file mode 100644 index c1044520d7..0000000000 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig deleted file mode 100644 index da04cab014..0000000000 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig deleted file mode 100644 index 723f6ca2bb..0000000000 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig deleted file mode 100644 index e6edd395e7..0000000000 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig deleted file mode 100644 index dcd606b0c2..0000000000 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,79 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig deleted file mode 100644 index 9987cde995..0000000000 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig deleted file mode 100644 index c0800c8d7d..0000000000 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig deleted file mode 100644 index 9691fd2bd4..0000000000 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig deleted file mode 100644 index 29ba692ca1..0000000000 --- a/configs/P1010RDB-PA_NAND_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig deleted file mode 100644 index 49351264cb..0000000000 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig deleted file mode 100644 index d8f87b5dac..0000000000 --- a/configs/P1010RDB-PA_NOR_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig deleted file mode 100644 index 9711082529..0000000000 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig deleted file mode 100644 index b31bdff00d..0000000000 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig deleted file mode 100644 index de2ac2235f..0000000000 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PA=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig deleted file mode 100644 index 66bdebbf99..0000000000 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig deleted file mode 100644 index 9f4876dd13..0000000000 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig deleted file mode 100644 index f2e40668ea..0000000000 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig deleted file mode 100644 index e85af32e2c..0000000000 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig deleted file mode 100644 index 45feab4ee4..0000000000 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,79 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig deleted file mode 100644 index 50b5c5f1c5..0000000000 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig deleted file mode 100644 index 3cd94f84ea..0000000000 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig deleted file mode 100644 index 17708dee47..0000000000 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig deleted file mode 100644 index ddfe7b43a1..0000000000 --- a/configs/P1010RDB-PB_NAND_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig deleted file mode 100644 index be455a0c8f..0000000000 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig deleted file mode 100644 index 6011f8a9d8..0000000000 --- a/configs/P1010RDB-PB_NOR_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig deleted file mode 100644 index 65f86fff60..0000000000 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig deleted file mode 100644 index ce3d7c4d6b..0000000000 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig deleted file mode 100644 index f71ee19ba6..0000000000 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xD0001000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1010RDB_PB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h deleted file mode 100644 index 8f709a6cac..0000000000 --- a/include/configs/P1010RDB.h +++ /dev/null @@ -1,766 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -/* - * P010 RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include -#define CONFIG_NAND_FSL_IFC - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#else -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#ifdef CONFIG_NXP_ESBC -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#else -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xD0001000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif -#endif - -#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#endif - -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" -#endif -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -/* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x52 - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#ifndef __ASSEMBLY__ -extern unsigned long get_sdram_size(void); -#endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -/* DDR3 Controller Settings */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* settings for DDR3 at 667MT/s */ -#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 -#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 -#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_667 0x00441210 -#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* Don't relocate CCSRBAR while in NAND_SPL */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus non-cacheable - * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable - * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ - -#define CONFIG_SYS_FLASH_BASE 0xee000000 -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ - FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ - | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ - | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) -#endif - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#if defined(CONFIG_TARGET_P1010RDB_PA) -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ - FTIM0_NAND_TWP(0x0C) | \ - FTIM0_NAND_TWCHT(0x04) | \ - FTIM0_NAND_TWH(0x05) -#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ - FTIM1_NAND_TWBE(0x1d) | \ - FTIM1_NAND_TRR(0x07) | \ - FTIM1_NAND_TRP(0x0c) -#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ - FTIM2_NAND_TREH(0x05) | \ - FTIM2_NAND_TWHRE(0x0f) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 -#endif - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull -#else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE -#endif - -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_A003399_NOR_WORKAROUND -#endif -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* - * Config the L2 Cache as L2 SRAM - */ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define I2C_PCA9557_ADDR1 0x18 -#define I2C_PCA9557_ADDR2 0x19 -#define I2C_PCA9557_BUS_NUM 0 -#define CONFIG_SYS_I2C_FSL - -/* I2C EEPROM */ -#if defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ -#endif -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* RTC */ -#define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * SPI interface will not be available in case of NAND boot SPI CS0 will be - * used for SLIC - */ -#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) -/* eSPI - Enhanced SPI */ -#endif - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif /* #ifdef CONFIG_FSL_SATA */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Environment - */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ -#endif -#endif -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ - || defined(CONFIG_FSL_SATA) -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p1010rdb.dtb\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - CONFIG_BOOTMODE - -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_BOOTMODE \ - "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ - "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ - "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_BOOTMODE \ - "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ - "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ - "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ - "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ - "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ - "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ - "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ - "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ - "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ - "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" -#endif - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */