diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6fc6ea8fef..dca83f4408 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV
 		Defines divider of platform clock(clock input to
 		eLBC controller).
 
-source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
 source "board/freescale/c29xpcie/Kconfig"
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
deleted file mode 100644
index 9bb667ab4f..0000000000
--- a/board/freescale/b4860qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_B4860QDS || TARGET_B4420QDS
-
-config SYS_BOARD
-	default "b4860qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "B4860QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
deleted file mode 100644
index 34ac099e44..0000000000
--- a/board/freescale/b4860qds/MAINTAINERS
+++ /dev/null
@@ -1,17 +0,0 @@
-B4860QDS BOARD
-M:	Ashish Kumar <ashish.kumar at nxp.com>
-S:	Maintained
-F:	board/freescale/b4860qds/
-F:	include/configs/B4860QDS.h
-F:	configs/B4420QDS_defconfig
-F:	configs/B4420QDS_NAND_defconfig
-F:	configs/B4420QDS_SPIFLASH_defconfig
-F:	configs/B4860QDS_defconfig
-F:	configs/B4860QDS_NAND_defconfig
-F:	configs/B4860QDS_SPIFLASH_defconfig
-F:	configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
-
-B4860QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta at nxp.com>
-S:	Maintained
-F:	configs/B4860QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
deleted file mode 100644
index c0ba2c0168..0000000000
--- a/board/freescale/b4860qds/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-else
-obj-y	+= b4860qds.o
-obj-$(CONFIG_TARGET_B4860QDS)	+= eth_b4860qds.o
-obj-$(CONFIG_TARGET_B4420QDS)	+= eth_b4860qds.o
-obj-$(CONFIG_PCI)	+= pci.o
-endif
-
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
deleted file mode 100644
index e10f948ae5..0000000000
--- a/board/freescale/b4860qds/b4860qds.c
+++ /dev/null
@@ -1,1274 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/idt8t49n222a_serdes_clk.h"
-#include "../common/zm7300.h"
-#include "b4860qds.h"
-#include "b4860qds_qixis.h"
-#include "b4860qds_crossbar_con.h"
-
-#define CLK_MUX_SEL_MASK	0x4
-#define ETH_PHY_CLK_OUT		0x4
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *const freq[] = {"100", "125", "156.25", "161.13",
-						"122.88", "122.88", "122.88"};
-	int clock;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-		QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw >= 0x8 && sw <= 0xE)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-		(int)QIXIS_READ(scver), qixis_read_tag(buf),
-		(int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference Clocks: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = (sw >> 5) & 7;
-	printf("Bank1=%sMHz ", freq[clock]);
-	sw = QIXIS_READ(brdcfg[4]);
-	clock = (sw >> 6) & 3;
-	printf("Bank2=%sMHz\n", freq[clock]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca(u8 ch)
-{
-	int ret;
-
-	/* Selecting proper channel via PCA*/
-	ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
-	if (ret) {
-		printf("PCA: failed to select proper channel.\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-/*
- * read_voltage from sensor on I2C bus
- * We use average of 4 readings, waiting for 532us befor another reading
- */
-#define WAIT_FOR_ADC	532	/* wait for 532 microseconds for ADC */
-#define NUM_READINGS	4	/* prefer to be power of 2 for efficiency */
-
-static inline int read_voltage(void)
-{
-	int i, ret, voltage_read = 0;
-	u16 vol_mon;
-
-	for (i = 0; i < NUM_READINGS; i++) {
-		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
-			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
-		if (ret) {
-			printf("VID: failed to read core voltage\n");
-			return ret;
-		}
-		if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
-			printf("VID: Core voltage sensor error\n");
-			return -1;
-		}
-		debug("VID: bus voltage reads 0x%04x\n", vol_mon);
-		/* LSB = 4mv */
-		voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
-		udelay(WAIT_FOR_ADC);
-	}
-	/* calculate the average */
-	voltage_read /= NUM_READINGS;
-
-	return voltage_read;
-}
-
-static int adjust_vdd(ulong vdd_override)
-{
-	int re_enable = disable_interrupts();
-	ccsr_gur_t __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 fusesr;
-	u8 vid;
-	int vdd_target, vdd_last;
-	int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
-	int ret;
-	unsigned int orig_i2c_speed;
-	unsigned long vdd_string_override;
-	char *vdd_string;
-	static const uint16_t vdd[32] = {
-		0,	/* unused */
-		9875,	/* 0.9875V */
-		9750,
-		9625,
-		9500,
-		9375,
-		9250,
-		9125,
-		9000,
-		8875,
-		8750,
-		8625,
-		8500,
-		8375,
-		8250,
-		8125,
-		10000,	/* 1.0000V */
-		10125,
-		10250,
-		10375,
-		10500,
-		10625,
-		10750,
-		10875,
-		11000,
-		0,	/* reserved */
-	};
-	struct vdd_drive {
-		u8 vid;
-		unsigned voltage;
-	};
-
-	ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
-	if (ret) {
-		printf("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* get the voltage ID from fuse status register */
-	fusesr = in_be32(&gur->dcfg_fusesr);
-	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
-		FSL_CORENET_DCFG_FUSESR_VID_MASK;
-	if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
-		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
-			FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
-	}
-	vdd_target = vdd[vid];
-	debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
-	      vid, vdd_target/10);
-
-	/* check override variable for overriding VDD */
-	vdd_string = env_get("b4qds_vdd_mv");
-	if (vdd_override == 0 && vdd_string &&
-	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
-		vdd_override = vdd_string_override;
-	if (vdd_override >= 819 && vdd_override <= 1212) {
-		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
-		debug("VDD override is %lu\n", vdd_override);
-	} else if (vdd_override != 0) {
-		printf("Invalid value.\n");
-	}
-
-	if (vdd_target == 0) {
-		printf("VID: VID not used\n");
-		ret = 0;
-		goto exit;
-	}
-
-	/*
-	 * Read voltage monitor to check real voltage.
-	 * Voltage monitor LSB is 4mv.
-	 */
-	vdd_last = read_voltage();
-	if (vdd_last < 0) {
-		printf("VID: abort VID adjustment\n");
-		ret = -1;
-		goto exit;
-	}
-
-	debug("VID: Core voltage is at %d mV\n", vdd_last);
-	ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
-	if (ret) {
-		printf("VID: I2c failed to switch channel to DPM\n");
-		ret = -1;
-		goto exit;
-	}
-
-	/* Round up to the value of step of Voltage regulator */
-	voltage = roundup(vdd_target, ZM_STEP);
-	debug("VID: rounded up voltage = %d\n", voltage);
-
-	/* lower the speed to 100kHz to access ZM7300 device */
-	debug("VID: Setting bus speed to 100KHz if not already set\n");
-	orig_i2c_speed = i2c_get_bus_speed();
-	if (orig_i2c_speed != 100000)
-		i2c_set_bus_speed(100000);
-
-	/* Read the existing level on board, if equal to requsted one,
-	   no need to re-set */
-	existing_voltage = zm_read_voltage();
-
-	/* allowing the voltage difference of one step 0.0125V acceptable */
-	if ((existing_voltage >= voltage) &&
-	    (existing_voltage < (voltage + ZM_STEP))) {
-		debug("VID: voltage already set as requested,returning\n");
-		ret = existing_voltage;
-		goto out;
-	}
-	debug("VID: Changing voltage for board from %dmV to %dmV\n",
-	      existing_voltage/10, voltage/10);
-
-	if (zm_disable_wp() < 0) {
-		ret = -1;
-		goto out;
-	}
-	/* Change Voltage: the change is done through all the steps in the
-	   way, to avoid reset to the board due to power good signal fail
-	   in big voltage change gap jump.
-	*/
-	if (existing_voltage > voltage) {
-		temp_voltage = existing_voltage - ZM_STEP;
-			while (temp_voltage >= voltage) {
-				ret = zm_write_voltage(temp_voltage);
-				if (ret == temp_voltage) {
-					temp_voltage -= ZM_STEP;
-				} else {
-					/* ZM7300 device failed to set
-					 * the voltage */
-					printf
-					("VID:Stepping down vol failed:%dmV\n",
-					 temp_voltage/10);
-				     ret = -1;
-				     goto out;
-				}
-			}
-	} else {
-		temp_voltage = existing_voltage + ZM_STEP;
-			while (temp_voltage < (voltage + ZM_STEP)) {
-				ret = zm_write_voltage(temp_voltage);
-				if (ret == temp_voltage) {
-					temp_voltage += ZM_STEP;
-				} else {
-					/* ZM7300 device failed to set
-					 * the voltage */
-					printf
-					("VID:Stepping up vol failed:%dmV\n",
-					 temp_voltage/10);
-				     ret = -1;
-				     goto out;
-				}
-			}
-	}
-
-	if (zm_enable_wp() < 0)
-		ret = -1;
-
-	/* restore the speed to 400kHz */
-out:	debug("VID: Restore the I2C bus speed to %dKHz\n",
-				orig_i2c_speed/1000);
-	i2c_set_bus_speed(orig_i2c_speed);
-	if (ret < 0)
-		goto exit;
-
-	ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
-	if (ret) {
-		printf("VID: I2c failed to switch channel\n");
-		ret = -1;
-		goto exit;
-	}
-	vdd_last = read_voltage();
-	select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-	if (vdd_last > 0)
-		printf("VID: Core voltage %d mV\n", vdd_last);
-	else
-		ret = -1;
-
-exit:
-	if (re_enable)
-		enable_interrupts();
-	return ret;
-}
-
-int configure_vsc3316_3308(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	unsigned int num_vsc16_con, num_vsc08_con;
-	u32 serdes1_prtcl, serdes2_prtcl;
-	int ret;
-	char buffer[HWCONFIG_BUFFER_SIZE];
-	char *buf = NULL;
-
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return 0;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		printf("SERDES2 is not enabled\n");
-		return 0;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2a:
-	case 0x2C:
-	case 0x2D:
-	case 0x2E:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B: SGMII
-			 * Lanes: C,D,E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar to use onboard SGMII PHYs:"
-				"srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_4sfp_sgmii_12_56,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_4sfp_sgmii_12_56,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-
-	case 0x01:
-	case 0x02:
-	case 0x04:
-	case 0x05:
-	case 0x06:
-	case 0x07:
-	case 0x08:
-	case 0x09:
-	case 0x0A:
-	case 0x0B:
-	case 0x0C:
-	case 0x2F:
-	case 0x30:
-	case 0x32:
-	case 0x33:
-	case 0x34:
-	case 0x39:
-	case 0x3A:
-	case 0x3C:
-	case 0x3D:
-	case 0x5C:
-	case 0x5D:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B: AURORA
-			 * Lanes: C,d: SGMII
-			 * Lanes: E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
-				" and CPRI. srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sfp_sgmii_aurora,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sfp_sgmii_aurora,
-					num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-
-#ifdef CONFIG_ARCH_B4420
-	case 0x17:
-	case 0x18:
-			/*
-			 * Configuration:
-			 * SERDES: 1
-			 * Lanes: A,B,C,D: SGMII
-			 * Lanes: E,F,G,H: CPRI
-			 */
-		debug("Configuring crossbar to use onboard SGMII PHYs:"
-				"srds_prctl:%x\n", serdes1_prtcl);
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sgmii_lane_cd, num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sgmii_lane_cd, num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-#endif
-
-	case 0x3E:
-	case 0x0D:
-	case 0x0E:
-	case 0x12:
-		num_vsc16_con = NUM_CON_VSC3316;
-		/* Configure VSC3316 crossbar switch */
-		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
-		if (!ret) {
-			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sfp, num_vsc16_con);
-			if (ret)
-				return ret;
-			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sfp, num_vsc16_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-	default:
-		printf("WARNING:VSC crossbars programming not supported for:%x"
-					" SerDes1 Protocol.\n", serdes1_prtcl);
-		return -1;
-	}
-
-	num_vsc08_con = NUM_CON_VSC3308;
-	/* Configure VSC3308 crossbar switch */
-	ret = select_i2c_ch_pca(I2C_CH_VSC3308);
-	switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
-	case 0x9d:
-#endif
-	case 0x9E:
-	case 0x9A:
-	case 0x98:
-	case 0x48:
-	case 0x49:
-	case 0x4E:
-	case 0x79:
-	case 0x7A:
-		if (!ret) {
-			ret = vsc3308_config(VSC3308_TX_ADDRESS,
-					vsc08_tx_amc, num_vsc08_con);
-			if (ret)
-				return ret;
-			ret = vsc3308_config(VSC3308_RX_ADDRESS,
-					vsc08_rx_amc, num_vsc08_con);
-			if (ret)
-				return ret;
-		} else {
-			return ret;
-		}
-		break;
-	case 0x80:
-	case 0x81:
-	case 0x82:
-	case 0x83:
-	case 0x84:
-	case 0x85:
-	case 0x86:
-	case 0x87:
-	case 0x88:
-	case 0x89:
-	case 0x8a:
-	case 0x8b:
-	case 0x8c:
-	case 0x8d:
-	case 0x8e:
-	case 0xb1:
-	case 0xb2:
-		if (!ret) {
-			/*
-			 * Extract hwconfig from environment since environment
-			 * is not setup properly yet
-			 */
-			env_get_f("hwconfig", buffer, sizeof(buffer));
-			buf = buffer;
-
-			if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
-						  "sfp_amc", "sfp", buf)) {
-#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
-				/* change default VSC3308 for XFI erratum */
-				ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
-						vsc08_tx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
-						vsc08_rx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-#else
-				ret = vsc3308_config(VSC3308_TX_ADDRESS,
-						vsc08_tx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config(VSC3308_RX_ADDRESS,
-						vsc08_rx_sfp, num_vsc08_con);
-				if (ret)
-					return ret;
-#endif
-			} else {
-				ret = vsc3308_config(VSC3308_TX_ADDRESS,
-						vsc08_tx_amc, num_vsc08_con);
-				if (ret)
-					return ret;
-
-				ret = vsc3308_config(VSC3308_RX_ADDRESS,
-						vsc08_rx_amc, num_vsc08_con);
-				if (ret)
-					return ret;
-			}
-
-		} else {
-			return ret;
-		}
-		break;
-	default:
-		printf("WARNING:VSC crossbars programming not supported for: %x"
-					" SerDes2 Protocol.\n", serdes2_prtcl);
-		return -1;
-	}
-
-	return 0;
-}
-
-static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
-{
-	u32 rst_err;
-
-	/* Steps For SerDes PLLs reset and reconfiguration
-	 * or PLL power-up procedure
-	 */
-	debug("CALIBRATE PLL:%d\n", pll_num);
-	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-			SRDS_RSTCTL_SDRST_B);
-	udelay(10);
-	clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-	udelay(10);
-	setbits_be32(&srds_regs->bank[pll_num].rstctl,
-			SRDS_RSTCTL_RST);
-	setbits_be32(&srds_regs->bank[pll_num].rstctl,
-		(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-		| SRDS_RSTCTL_SDRST_B));
-
-	udelay(20);
-
-	/* Check whether PLL has been locked or not */
-	rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
-				SRDS_RSTCTL_RSTERR;
-	rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
-	debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
-	if (rst_err)
-		return rst_err;
-
-	return rst_err;
-}
-
-static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
-{
-	int ret = 0;
-	u32 fcap, dcbias, bcap, pllcr1, pllcr0;
-
-	if (calibrate_pll(srds_regs, pll_num)) {
-		/* STEP 1 */
-		/* Read fcap, dcbias and bcap value */
-		clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-				SRDS_PLLCR0_DCBIAS_OUT_EN);
-		fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_FCAP;
-		fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
-		bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_BCAP_EN;
-		bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
-		setbits_be32(&srds_regs->bank[pll_num].pllcr0,
-				SRDS_PLLCR0_DCBIAS_OUT_EN);
-		dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
-					SRDS_PLLSR2_DCBIAS;
-		dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-		debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
-					bcap, fcap, dcbias);
-		if (fcap == 0 && bcap == 1) {
-			/* Step 3 */
-			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_EN);
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_OVD);
-			if (calibrate_pll(srds_regs, pll_num)) {
-				/*save the fcap, dcbias and bcap values*/
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OUT_EN);
-				fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
-					& SRDS_PLLSR2_FCAP;
-				fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
-				bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
-					& SRDS_PLLSR2_BCAP_EN;
-				bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
-				setbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OUT_EN);
-				dcbias = in_be32
-					(&srds_regs->bank[pll_num].pllsr2) &
-							SRDS_PLLSR2_DCBIAS;
-				dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
-
-				/* Step 4*/
-				clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BYP_CAL);
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BCAP_EN);
-				setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_BCAP_OVD);
-				/* change the fcap and dcbias to the saved
-				 * values from Step 3 */
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-							SRDS_PLLCR1_PLL_FCAP);
-				pllcr1 = (in_be32
-					(&srds_regs->bank[pll_num].pllcr1)|
-					(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
-				out_be32(&srds_regs->bank[pll_num].pllcr1,
-							pllcr1);
-				clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OVRD);
-				pllcr0 = (in_be32
-				(&srds_regs->bank[pll_num].pllcr0)|
-				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
-				out_be32(&srds_regs->bank[pll_num].pllcr0,
-							pllcr0);
-				ret = calibrate_pll(srds_regs, pll_num);
-				if (ret)
-					return ret;
-			} else {
-				goto out;
-			}
-		} else { /* Step 5 */
-			clrbits_be32(&srds_regs->bank[pll_num].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				 | SRDS_RSTCTL_SDRST_B));
-			udelay(10);
-			/* Change the fcap, dcbias, and bcap to the
-			 * values from Step 1 */
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BYP_CAL);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-						SRDS_PLLCR1_PLL_FCAP);
-			pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
-				(fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
-			out_be32(&srds_regs->bank[pll_num].pllcr1,
-						pllcr1);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
-						SRDS_PLLCR0_DCBIAS_OVRD);
-			pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
-				(dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
-			out_be32(&srds_regs->bank[pll_num].pllcr0,
-						pllcr0);
-			clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_EN);
-			setbits_be32(&srds_regs->bank[pll_num].pllcr1,
-					SRDS_PLLCR1_BCAP_OVD);
-			ret = calibrate_pll(srds_regs, pll_num);
-			if (ret)
-				return ret;
-		}
-	}
-out:
-	return 0;
-}
-
-static int check_serdes_pll_locks(void)
-{
-	serdes_corenet_t *srds1_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	serdes_corenet_t *srds2_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
-	int i, ret1, ret2;
-
-	debug("\nSerDes1 Lock check\n");
-	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-		ret1 = check_pll_locks(srds1_regs, i);
-		if (ret1) {
-			printf("SerDes1, PLL:%d didnt lock\n", i);
-			return ret1;
-		}
-	}
-	debug("\nSerDes2 Lock check\n");
-	for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-		ret2 = check_pll_locks(srds2_regs, i);
-		if (ret2) {
-			printf("SerDes2, PLL:%d didnt lock\n", i);
-			return ret2;
-		}
-	}
-
-	return 0;
-}
-
-int config_serdes1_refclks(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 serdes1_prtcl, lane;
-	unsigned int flag_sgmii_aurora_prtcl = 0;
-	int i;
-	int ret = 0;
-
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return -1;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	/* To prevent generation of reset request from SerDes
-	 * while changing the refclks, By setting SRDS_RST_MSK bit,
-	 * SerDes reset event cannot cause a reset request
-	 */
-	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
-	/* Reconfigure IDT idt8t49n222a device for CPRI to work
-	 * For this SerDes1's Refclk1 and refclk2 need to be set
-	 * to 122.88MHz
-	 */
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2A:
-	case 0x2C:
-	case 0x2D:
-	case 0x2E:
-	case 0x01:
-	case 0x02:
-	case 0x04:
-	case 0x05:
-	case 0x06:
-	case 0x07:
-	case 0x08:
-	case 0x09:
-	case 0x0A:
-	case 0x0B:
-	case 0x0C:
-	case 0x2F:
-	case 0x30:
-	case 0x32:
-	case 0x33:
-	case 0x34:
-	case 0x39:
-	case 0x3A:
-	case 0x3C:
-	case 0x3D:
-	case 0x5C:
-	case 0x5D:
-		debug("Configuring idt8t49n222a for CPRI SerDes clks:"
-			" for srds_prctl:%x\n", serdes1_prtcl);
-		ret = select_i2c_ch_pca(I2C_CH_IDT);
-		if (!ret) {
-			ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
-					SERDES_REFCLK_122_88,
-					SERDES_REFCLK_122_88, 0);
-			if (ret) {
-				printf("IDT8T49N222A configuration failed.\n");
-				goto out;
-			} else
-				debug("IDT8T49N222A configured.\n");
-		} else {
-			goto out;
-		}
-		select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-		/* Change SerDes1's Refclk1 to 125MHz for on board
-		 * SGMIIs or Aurora to work
-		 */
-		for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
-			enum srds_prtcl lane_prtcl = serdes_get_prtcl
-						(0, serdes1_prtcl, lane);
-			switch (lane_prtcl) {
-			case SGMII_FM1_DTSEC1:
-			case SGMII_FM1_DTSEC2:
-			case SGMII_FM1_DTSEC3:
-			case SGMII_FM1_DTSEC4:
-			case SGMII_FM1_DTSEC5:
-			case SGMII_FM1_DTSEC6:
-			case AURORA:
-				flag_sgmii_aurora_prtcl++;
-				break;
-			default:
-				break;
-			}
-		}
-
-		if (flag_sgmii_aurora_prtcl)
-			QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-
-		/* Steps For SerDes PLLs reset and reconfiguration after
-		 * changing SerDes's refclks
-		 */
-		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-			debug("For PLL%d reset and reconfiguration after"
-			       " changing refclks\n", i+1);
-			clrbits_be32(&srds_regs->bank[i].rstctl,
-					SRDS_RSTCTL_SDRST_B);
-			udelay(10);
-			clrbits_be32(&srds_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-			udelay(10);
-			setbits_be32(&srds_regs->bank[i].rstctl,
-					SRDS_RSTCTL_RST);
-			setbits_be32(&srds_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				| SRDS_RSTCTL_SDRST_B));
-		}
-		break;
-	default:
-		printf("WARNING:IDT8T49N222A configuration not"
-			" supported for:%x SerDes1 Protocol.\n",
-			serdes1_prtcl);
-	}
-
-out:
-	/* Clearing SRDS_RST_MSK bit as now
-	 * SerDes reset event can cause a reset request
-	 */
-	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-	return ret;
-}
-
-int config_serdes2_refclks(void)
-{
-	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes_corenet_t *srds2_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
-	u32 serdes2_prtcl;
-	int ret = 0;
-	int i;
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		debug("SERDES2 is not enabled\n");
-		return -ENODEV;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	/* To prevent generation of reset request from SerDes
-	 * while changing the refclks, By setting SRDS_RST_MSK bit,
-	 * SerDes reset event cannot cause a reset request
-	 */
-	setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-
-	/* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
-	 * For this SerDes2's Refclk1 need to be set to 100MHz
-	 */
-	switch (serdes2_prtcl) {
-#ifdef CONFIG_ARCH_B4420
-	case 0x9d:
-#endif
-	case 0x9E:
-	case 0x9A:
-		/* fallthrough */
-	case 0xb1:
-	case 0xb2:
-		debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
-			serdes2_prtcl);
-		ret = select_i2c_ch_pca(I2C_CH_IDT);
-		if (!ret) {
-			ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
-					SERDES_REFCLK_100,
-					SERDES_REFCLK_156_25, 0);
-			if (ret) {
-				printf("IDT8T49N222A configuration failed.\n");
-				goto out;
-			} else
-				debug("IDT8T49N222A configured.\n");
-		} else {
-			goto out;
-		}
-		select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-		/* Steps For SerDes PLLs reset and reconfiguration after
-		 * changing SerDes's refclks
-		 */
-		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
-			clrbits_be32(&srds2_regs->bank[i].rstctl,
-					SRDS_RSTCTL_SDRST_B);
-			udelay(10);
-			clrbits_be32(&srds2_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
-			udelay(10);
-			setbits_be32(&srds2_regs->bank[i].rstctl,
-					SRDS_RSTCTL_RST);
-			setbits_be32(&srds2_regs->bank[i].rstctl,
-				(SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
-				| SRDS_RSTCTL_SDRST_B));
-
-			udelay(10);
-		}
-		break;
-	default:
-		printf("IDT configuration not supported for:%x S2 Protocol.\n",
-			serdes2_prtcl);
-	}
-
-out:
-	/* Clearing SRDS_RST_MSK bit as now
-	 * SerDes reset event can cause a reset request
-	 */
-	clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
-	return ret;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-	int ret;
-	u32 svr = SVR_SOC_VER(get_svr());
-
-	/* Create law for MAPLE only for personalities having MAPLE */
-	if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
-	    (svr == SVR_B4420) || (svr == SVR_B4220)) {
-		set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
-			     LAW_TRGT_IF_MAPLE);
-	}
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	/*
-	 * Adjust core voltage according to voltage ID
-	 * This function changes I2C mux to channel 2.
-	 */
-	if (adjust_vdd(0) < 0)
-		printf("Warning: Adjusting core voltage failed\n");
-
-	/* SerDes1 refclks need to be set again, as default clks
-	 * are not suitable for CPRI and onboard SGMIIs to work
-	 * simultaneously.
-	 * This function will set SerDes1's Refclk1 and refclk2
-	 * as per SerDes1 protocols
-	 */
-	if (config_serdes1_refclks())
-		printf("SerDes1 Refclks couldn't set properly.\n");
-	else
-		printf("SerDes1 Refclks have been set.\n");
-
-	/* SerDes2 refclks need to be set again, as default clks
-	 * are not suitable for PCIe SATA to work
-	 * This function will set SerDes2's Refclk1 and refclk2
-	 * for SerDes2 protocols having PCIe in them
-	 * for PCIe SATA to work
-	 */
-	ret = config_serdes2_refclks();
-	if (!ret)
-		printf("SerDes2 Refclks have been set.\n");
-	else if (ret == -ENODEV)
-		printf("SerDes disable, Refclks couldn't change.\n");
-	else
-		printf("SerDes2 Refclk reconfiguring failed.\n");
-
-#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
-			defined(CONFIG_SYS_FSL_ERRATUM_A006475)
-	/* Rechecking the SerDes locks after all SerDes configurations
-	 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
-	 * and at cold temperatures.
-	 * Following sequence ensure the proper locking of SerDes PLLs.
-	 */
-	if (SVR_MAJ(get_svr()) == 1) {
-		if (check_serdes_pll_locks())
-			printf("SerDes plls still not locked properly.\n");
-		else
-			printf("SerDes plls have been locked well.\n");
-	}
-#endif
-
-	/* Configure VSC3316 and VSC3308 crossbar switches */
-	if (configure_vsc3316_3308())
-		printf("VSC:failed to configure VSC3316/3308.\n");
-	else
-		printf("VSC:VSC3316/3308 successfully configured.\n");
-
-	select_i2c_ch_pca(I2C_CH_DEFAULT);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((sysclk_conf & 0x0C) >> 2) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (ddrclk_conf & 0x03) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-static int serdes_refclock(u8 sw, u8 sdclk)
-{
-	unsigned int clock;
-	int ret = -1;
-	u8 brdcfg4;
-
-	if (sdclk == 1) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
-			return SRDS_PLLCR0_RFCK_SEL_125;
-		else
-			clock = (sw >> 5) & 7;
-	} else
-		clock = (sw >> 6) & 3;
-
-	switch (clock) {
-	case 0:
-		ret = SRDS_PLLCR0_RFCK_SEL_100;
-		break;
-	case 1:
-		ret = SRDS_PLLCR0_RFCK_SEL_125;
-		break;
-	case 2:
-		ret = SRDS_PLLCR0_RFCK_SEL_156_25;
-		break;
-	case 3:
-		ret = SRDS_PLLCR0_RFCK_SEL_161_13;
-		break;
-	case 4:
-	case 5:
-	case 6:
-		ret = SRDS_PLLCR0_RFCK_SEL_122_88;
-		break;
-	default:
-		ret = -1;
-		break;
-	}
-
-	return ret;
-}
-
-#define NUM_SRDS_BANKS	2
-
-int misc_init_r(void)
-{
-	u8 sw;
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 actual[NUM_SRDS_BANKS];
-	unsigned int i;
-	int clock;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = serdes_refclock(sw, 1);
-	if (clock >= 0)
-		actual[0] = clock;
-	else
-		printf("Warning: SDREFCLK1 switch setting is unsupported\n");
-
-	sw = QIXIS_READ(brdcfg[4]);
-	clock = serdes_refclock(sw, 2);
-	if (clock >= 0)
-		actual[1] = clock;
-	else
-		printf("Warning: SDREFCLK2 switch setting unsupported\n");
-
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 pllcr0 = srds_regs->bank[i].pllcr0;
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("Warning: SERDES bank %u expects reference clock"
-			       " %sMHz, but actual is %sMHz\n", i + 1,
-			       serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
-
-/*
- * Dump board switch settings.
- * The bits that cannot be read/sampled via some FPGA or some
- * registers, they will be displayed as
- * underscore in binary format. mask[] has those bits.
- * Some bits are calculated differently than the actual switches
- * if booting with overriding by FPGA.
- */
-void qixis_dump_switch(void)
-{
-	int i;
-	u8 sw[5];
-
-	/*
-	 * Any bit with 1 means that bit cannot be reverse engineered.
-	 * It will be displayed as _ in binary format.
-	 */
-	static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
-	char buf[10];
-	u8 brdcfg[16], dutcfg[16];
-
-	for (i = 0; i < 16; i++) {
-		brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
-		dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
-	}
-
-	sw[0] = ((brdcfg[0] & 0x0f) << 4)	| \
-		(brdcfg[9] & 0x08);
-	sw[1] = ((dutcfg[1] & 0x01) << 7)	| \
-		((dutcfg[2] & 0x07) << 4)       | \
-		((dutcfg[6] & 0x10) >> 1)       | \
-		((dutcfg[6] & 0x80) >> 5)       | \
-		((dutcfg[1] & 0x40) >> 5)       | \
-		(dutcfg[6] & 0x01);
-	sw[2] = dutcfg[0];
-	sw[3] = 0;
-	sw[4] = ((brdcfg[1] & 0x30) << 2)	| \
-		((brdcfg[1] & 0xc0) >> 2)	| \
-		(brdcfg[1] & 0x0f);
-
-	puts("DIP switch settings:\n");
-	for (i = 0; i < 5; i++) {
-		printf("SW%d         = 0b%s (0x%02x)\n",
-			i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
-	}
-}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
deleted file mode 100644
index 4a8e91b58f..0000000000
--- a/board/freescale/b4860qds/b4860qds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
deleted file mode 100644
index b9d59c23be..0000000000
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CROSSBAR_CONNECTIONS_H__
-#define __CROSSBAR_CONNECTIONS_H__
-
-#define NUM_CON_VSC3316	8
-#define NUM_CON_VSC3308	4
-
-static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
-				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
-
-static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
-				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {2, 14}, {12, 15},
-				{-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {5, 14}, {4, 15},
-				{-1, -1}, {-1, -1} };
-
-static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
-				{7, 8}, {9, 0}, {5, 14},
-				{4, 15}, {2, 12}, {12, 13} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
-			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
-				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
-
-static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
-				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 3}, {15, 12},
-				{-1, -1}, {-1, -1} };
-
-static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 11}, {15, 10},
-				{-1, -1}, {-1, -1} };
-
-static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
-				{7, 8}, {1, 9}, {14, 11},
-				{15, 10}, {13, 3}, {12, 12} };
-
-#ifdef CONFIG_ARCH_B4420
-static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-#endif
-
-static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
-			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-
-static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
-
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
-
-static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
-
-static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
-
-#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
deleted file mode 100644
index d4299d8af1..0000000000
--- a/board/freescale/b4860qds/b4860qds_qixis.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __B4860QDS_QIXIS_H__
-#define __B4860QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for B4860QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* CLK */
-#define QIXIS_CLK_66		0x0
-#define QIXIS_CLK_100		0x1
-#define QIXIS_CLK_125		0x2
-#define QIXIS_CLK_133		0x3
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-
-/* SGMII */
-#define PHY_BASE_ADDR		0x18
-#define PORT_NUM		0x04
-#define REGNUM			0x00
-#endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
deleted file mode 100644
index 05377bac5b..0000000000
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
deleted file mode 100644
index 597d3914ca..0000000000
--- a/board/freescale/b4860qds/b4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x2A_0x98
-140e0018 0f001218 00000000 00000000
-54980000 9000a000 e8104000 a9000000
-01000000 00000000 00000000 0001b1f8
-00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
deleted file mode 100644
index d3aa349ddf..0000000000
--- a/board/freescale/b4860qds/ddr.c
+++ /dev/null
@@ -1,267 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <fsl_ddr.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 2,
-	.rank_density = 2147483648u,
-	.capacity = 4294967296u,
-	.primary_sdram_width = 64,
-	.ec_sdram_width = 8,
-	.registered_dimm = 0,
-	.mirrored_dimm = 1,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 2,	/* ECC */
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1071,
-	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
-	.taa_ps = 13910,
-	.twr_ps = 15000,
-	.trcd_ps = 13910,
-	.trrd_ps = 6000,
-	.trp_ps = 13910,
-	.tras_ps = 34000,
-	.trc_ps = 48910,
-	.trfc_ps = 260000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 35000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "RAW timing DDR";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
-	{2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
-	{2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
-	{1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
-	{1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
-	{1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twot_en = pbsp_highest->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x3e;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	puts("Initializing....using SPD\n");
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size =  fsl_ddr_sdram_size();
-#endif
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
-			  unsigned int dbw_cap_adj[])
-{
-	int i, j;
-	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
-	unsigned long long rank_density, ctlr_density = 0;
-
-	current_mem_base = 0ull;
-	total_mem = 0;
-	/*
-	 * This board has soldered DDR chips. DDRC1 has two rank.
-	 * DDRC2 has only one rank.
-	 * Assigning DDRC2 to lower address and DDRC1 to higher address.
-	 */
-	if (pinfo->memctl_opts[0].memctl_interleaving) {
-		rank_density = pinfo->dimm_params[0][0].rank_density >>
-					dbw_cap_adj[0];
-		ctlr_density = rank_density;
-
-		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
-		      rank_density, ctlr_density);
-		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
-			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
-			case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			case FSL_DDR_PAGE_INTERLEAVING:
-			case FSL_DDR_BANK_INTERLEAVING:
-			case FSL_DDR_SUPERBANK_INTERLEAVING:
-				total_ctlr_mem = 2 * ctlr_density;
-				break;
-			default:
-				panic("Unknown interleaving mode");
-			}
-			pinfo->common_timing_params[i].base_address =
-						current_mem_base;
-			pinfo->common_timing_params[i].total_mem =
-						total_ctlr_mem;
-			total_mem = current_mem_base + total_ctlr_mem;
-			debug("ctrl %d base 0x%llx\n", i, current_mem_base);
-			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-		}
-	} else {
-		/*
-		 * Simple linear assignment if memory
-		 * controllers are not interleaved.
-		 */
-		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
-			total_ctlr_mem = 0;
-			pinfo->common_timing_params[i].base_address =
-						current_mem_base;
-			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
-				/* Compute DIMM base addresses. */
-				unsigned long long cap =
-					pinfo->dimm_params[i][j].capacity;
-				pinfo->dimm_params[i][j].base_address =
-					current_mem_base;
-				debug("ctrl %d dimm %d base 0x%llx\n",
-				      i, j, current_mem_base);
-				current_mem_base += cap;
-				total_ctlr_mem += cap;
-			}
-			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
-			pinfo->common_timing_params[i].total_mem =
-							total_ctlr_mem;
-			total_mem += total_ctlr_mem;
-		}
-	}
-	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
-
-	return total_mem;
-}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
deleted file mode 100644
index 6d5f3d1fda..0000000000
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Sandeep Kumar Singh <sandeep at freescale.com>
- */
-
-/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
-
-/*
- * This file handles the board muxing between the Fman Ethernet MACs and
- * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
- * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
- * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
- * one Fman device on B4860. The SERDES configuration is used to determine
- * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
- * to which PHYs. So for a given Fman MAC, there is one and only PHY it
- * connects to. MACs cannot be routed to PHYs dynamically. This configuration
- * is done at boot time by reading SERDES protocol from RCW.
- */
-
-#include <common.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fdt_support.h>
-#include <fsl_dtsec.h>
-
-#include "../common/ngpixis.h"
-#include "../common/fman.h"
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-#define EMI_NONE       0xFFFFFFFF
-
-#ifdef CONFIG_FMAN_ENET
-
-/*
- * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
- * lane at index is mapped to slot number n. A value of '0' will mean
- * that the mapping must be determined dynamically, or that the lane maps to
- * something other than a board slot
- */
-static u8 lane_to_slot[] = {
-	0, 0, 0, 0,
-	0, 0, 0, 0,
-	1, 1, 1, 1,
-	0, 0, 0, 0
-};
-
-/*
- * This function initializes the lane_to_slot[] array. It reads RCW to check
- * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
- * lane_to_slot[] accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	unsigned int  serdes2_prtcl;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Initializing lane to slot: Serdes2 protocol: %x\n",
-			serdes2_prtcl);
-
-	switch (serdes2_prtcl) {
-	case 0x17:
-	case 0x18:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: SGMII
-		 * Lanes: E,F: Aur
-		 * Lanes: G,H: SRIO
-		 */
-	case 0x91:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: SGMII
-		 * Lanes: C,D: SRIO2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x93:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: SGMII
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x98:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: XAUI2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x9a:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: PCI
-		 * Lanes: C,D: SGMII
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0x9e:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: PCI
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-	case 0xb1:
-	case 0xb2:
-	case 0x8c:
-	case 0x8d:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B,C,D: PCI
-		 * Lanes: E,F: SGMII 3&4
-		 * Lanes: G,H: XFI
-		 */
-	case 0xc2:
-		/*
-		 * Configuration:
-		 * SERDES: 2
-		 * Lanes: A,B: SGMII
-		 * Lanes: C,D: SRIO2
-		 * Lanes: E,F,G,H: XAUI2
-		 */
-		lane_to_slot[12] = 2;
-		lane_to_slot[13] = lane_to_slot[12];
-		lane_to_slot[14] = lane_to_slot[12];
-		lane_to_slot[15] = lane_to_slot[12];
-		break;
-
-	default:
-		printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
-				serdes2_prtcl);
-			break;
-	}
-	return;
-}
-
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	struct memac_mdio_info tg_memac_mdio_info;
-	unsigned int i;
-	unsigned int  serdes1_prtcl, serdes2_prtcl;
-	int qsgmii;
-	struct mii_dev *bus;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	if (!serdes1_prtcl) {
-		printf("SERDES1 is not enabled\n");
-		return 0;
-	}
-	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
-
-	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
-		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	if (!serdes2_prtcl) {
-		printf("SERDES2 is not enabled\n");
-		return 0;
-	}
-	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
-
-	printf("Initializing Fman\n");
-
-	initialize_lane_to_slot();
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	tg_memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the real 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tg_memac_mdio_info);
-
-	/*
-	 * Program the two on board DTSEC PHY addresses assuming that they are
-	 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
-	 * 6 to on board SGMII phys
-	 */
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-
-	switch (serdes1_prtcl) {
-	case 0x29:
-	case 0x2a:
-		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
-		debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
-		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
-		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC5,
-				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6,
-				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		break;
-#ifdef CONFIG_ARCH_B4420
-	case 0x17:
-	case 0x18:
-		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
-		debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
-		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
-		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		/* Fixing Serdes clock by programming FPGA register */
-		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
-		break;
-#endif
-	default:
-		printf("Fman:  Unsupported SerDes1 Protocol 0x%02x\n",
-				serdes1_prtcl);
-		break;
-	}
-	switch (serdes2_prtcl) {
-	case 0x17:
-	case 0x18:
-		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
-		break;
-	case 0x48:
-	case 0x49:
-		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
-		break;
-	case 0xb1:
-	case 0xb2:
-	case 0x8c:
-	case 0x8d:
-		debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
-		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
-		/*
-		 * XFI does not need a PHY to work, but to make U-Boot
-		 * happy, assign a fake PHY address for a XFI port.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 0);
-		fm_info_set_phy_address(FM1_10GEC2, 1);
-		break;
-	case 0x98:
-		/* XAUI in Slot1 and Slot2 */
-		debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
-		      CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC1,
-					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-		debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
-		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2,
-					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		break;
-	case 0x9E:
-		/* XAUI in Slot2 */
-		debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
-		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2,
-					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
-		break;
-	default:
-		printf("Fman:  Unsupported SerDes2 Protocol 0x%02x\n",
-				serdes2_prtcl);
-		break;
-	}
-
-	/*set PHY address for QSGMII Riser Card on slot2*/
-	bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
-
-	if (qsgmii) {
-		switch (serdes2_prtcl) {
-		case 0xb2:
-		case 0x8d:
-			fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
-			fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			fm_info_set_mdio(i,
-				miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-			break;
-		case PHY_INTERFACE_MODE_NONE:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: DTSEC%u set to unknown interface %i\n",
-					idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		int idx = i - FM1_10GEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			fm_info_set_mdio(i,
-					 miiphy_get_dev_by_name
-					 (DEFAULT_FM_TGEC_MDIO_NAME));
-			break;
-		case PHY_INTERFACE_MODE_NONE:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: TGEC%u set to unknown interface %i\n",
-			       idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	int phy;
-	char alias[32];
-	struct fixed_link f_link;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-
-	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		phy = fm_info_get_phy_address(port);
-
-		sprintf(alias, "phy_sgmii_%x", phy);
-		fdt_set_phy_handle(fdt, compat, addr, alias);
-		fdt_status_okay_by_alias(fdt, alias);
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		/* check if it's XFI interface for 10g */
-		switch (prtcl2) {
-		case 0x80:
-		case 0x81:
-		case 0x82:
-		case 0x83:
-		case 0x84:
-		case 0x85:
-		case 0x86:
-		case 0x87:
-		case 0x88:
-		case 0x89:
-		case 0x8a:
-		case 0x8b:
-		case 0x8c:
-		case 0x8d:
-		case 0x8e:
-		case 0xb1:
-		case 0xb2:
-			f_link.phy_id = port;
-			f_link.duplex = 1;
-			f_link.link_speed = 10000;
-			f_link.pause = 0;
-			f_link.asym_pause = 0;
-
-			fdt_delprop(fdt, offset, "phy-handle");
-			fdt_setprop(fdt, offset, "fixed-link", &f_link,
-				    sizeof(f_link));
-			break;
-		case 0x98: /* XAUI interface */
-			strcpy(alias, "phy_xaui_slot1");
-			fdt_status_okay_by_alias(fdt, alias);
-
-			strcpy(alias, "phy_xaui_slot2");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		case 0x9e: /* XAUI interface */
-		case 0x9a:
-		case 0x93:
-		case 0x91:
-			strcpy(alias, "phy_xaui_slot1");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		case 0x97: /* XAUI interface */
-		case 0xc3:
-			strcpy(alias, "phy_xaui_slot2");
-			fdt_status_okay_by_alias(fdt, alias);
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-/*
- * Set status to disabled for unused ethernet node
- */
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i;
-	char alias[32];
-
-	for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_NONE:
-			sprintf(alias, "ethernet%u", i);
-			fdt_status_disabled_by_alias(fdt, alias);
-			break;
-		default:
-			break;
-		}
-	}
-}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
deleted file mode 100644
index b39d720068..0000000000
--- a/board/freescale/b4860qds/law.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
deleted file mode 100644
index 45dd461e77..0000000000
--- a/board/freescale/b4860qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
deleted file mode 100644
index fe5ce35013..0000000000
--- a/board/freescale/b4860qds/spl.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include "../common/qixis.h"
-#include "b4860qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((sysclk_conf & 0x0C) >> 2) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (ddrclk_conf & 0x03) {
-	case QIXIS_CLK_100:
-		return 100000000;
-	case QIXIS_CLK_125:
-		return 125000000;
-	case QIXIS_CLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, uart_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("" : : : "memory");
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	uart_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     uart_clk / 16 / CONFIG_BAUDRATE);
-
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifndef CONFIG_SPL_NAND_BOOT
-	env_init();
-	env_relocate();
-#else
-	/* relocate environment function pointers etc. */
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-#endif
-
-	i2c_init_all();
-
-	puts("\n\n");
-
-	dram_init();
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
deleted file mode 100644
index 68e2295cb5..0000000000
--- a/board/freescale/b4860qds/tlb.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
-	 * space is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 11, BOOKE_PAGESZ_64K, 1),
-#endif
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_4K, 1),
-
-	/*
-	 * *I*G - SRIO
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for SRIO2.
-	 */
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
-	/* *I*G* - SRIO1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
-	/* *I*G* - SRIO2 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
-		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 16, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
-	 * fetching ucode and ENV from master
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 17, BOOKE_PAGESZ_1M, 1),
-#endif
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 17, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
deleted file mode 100644
index 6fcb51a1cd..0000000000
--- a/configs/B4420QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
deleted file mode 100644
index 5dc72cb3f2..0000000000
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
deleted file mode 100644
index 5f9a88adfa..0000000000
--- a/configs/B4420QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4420QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
deleted file mode 100644
index 0874acd83e..0000000000
--- a/configs/B4860QDS_NAND_defconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 4d7bf5dc39..0000000000
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
deleted file mode 100644
index 566076543f..0000000000
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 58195adcbc..0000000000
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
deleted file mode 100644
index 68ff6ed953..0000000000
--- a/configs/B4860QDS_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_B4860QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
deleted file mode 100644
index a515bf9530..0000000000
--- a/include/configs/B4860QDS.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * B4860 QDS board configuration file
- */
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
-#ifndef CONFIG_MTD_RAW_NAND
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO		0x40000
-#define CONFIG_SPL_MAX_SIZE		0x28000
-#define RESET_VECTOR_OFFSET		0x27FFC
-#define BOOT_PAGE_OFFSET		0x27000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-#endif
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
-#ifndef CONFIG_ARCH_B4420
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#endif
-
-/* I2C bus multiplexer */
-#define I2C_MUX_PCA_ADDR                0x77
-
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
-#define I2C_CH_DEFAULT                  0x8
-#define I2C_CH_VSC3316                  0xc
-#define I2C_CH_VSC3308                  0xd
-
-#define VSC3316_TX_ADDRESS              0x70
-#define VSC3316_RX_ADDRESS              0x71
-#define VSC3308_TX_ADDRESS              0x02
-#define VSC3308_RX_ADDRESS              0x03
-
-/* IDT clock synthesizers */
-#define CONFIG_IDT8T49N222A
-#define I2C_CH_IDT                     0x9
-
-#define IDT_SERDES1_ADDRESS            0x6E
-#define IDT_SERDES2_ADDRESS            0x6C
-
-/* Voltage monitor on channel 2*/
-#define I2C_MUX_CH_VOL_MONITOR		0xa
-#define I2C_VOL_MONITOR_ADDR		0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
-
-#define CONFIG_ZM7300
-#define I2C_MUX_CH_DPM			0xa
-#define I2C_DPM_ADDR			0x28
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV          0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB			/* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
-#endif
-
-#if 0
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
-#endif
-
-/*
- *  Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
-#define CONFIG_SYS_L3_SIZE		256 << 10
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
-#endif
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM	0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
-
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS1	0x51
-#define SPD_EEPROM_ADDRESS2	0x53
-
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE	0xe0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
-				+ 0x8000000) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
-				FTIM0_NOR_TEADC(0x04) | \
-				FTIM0_NOR_TEAHC(0x20))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
-				FTIM1_NOR_TRAD_NOR(0x1A) |\
-				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
-				FTIM2_NOR_TCH(0x0E) | \
-				FTIM2_NOR_TWPH(0x0E) | \
-				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
-#define CONFIG_FSL_QIXIS_V2
-#define QIXIS_BASE		0xffdf0000
-#ifdef CONFIG_PHYS_64BIT
-#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
-#else
-#define QIXIS_BASE_PHYS		QIXIS_BASE
-#endif
-#define QIXIS_LBMAP_SWITCH		0x01
-#define QIXIS_LBMAP_MASK		0x0f
-#define QIXIS_LBMAP_SHIFT		0
-#define QIXIS_LBMAP_DFLTBANK		0x00
-#define QIXIS_LBMAP_ALTBANK		0x02
-#define QIXIS_RST_CTL_RESET		0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 \
-				| CSPR_MSEL_GPCM \
-				| CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
-					FTIM0_GPCM_TEADC(0x0e) | \
-					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
-					FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x8) | \
-					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
-				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x07) | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0x0e)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
-					FTIM2_NAND_TREH(0x0a) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW		11
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
-#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
-
-/*
- * RapidIO
- */
-#ifdef CONFIG_SYS_SRIO
-#ifdef CONFIG_SRIO1
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
-#endif
-
-#ifdef CONFIG_SRIO2
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
-#endif
-#endif
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * MAPLE
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
-#else
-#define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
-#endif
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	25
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE	0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE	0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE	CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE	(CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	25
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-
-#define CONFIG_SYS_DPAA_RMAN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 545KB (1089 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x10
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x11
-#endif
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
-#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
-
-/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
-#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
-
-#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
-#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
-#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
-#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
-
-#define CONFIG_ETHPRIME		"FM1 at DTSEC1"
-#endif
-
-#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
-* USB
-*/
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-#define __USB_PHY_TYPE	ulpi
-
-#ifdef CONFIG_ARCH_B4860
-#define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
-			"bank_intlv=cs0_cs1;"	\
-			"en_cpc:cpc2;"
-#else
-#define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
-#endif
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	HWCONFIG						\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
-	"tftpflash=tftpboot $loadaddr $uboot && "		\
-	"protect off $ubootaddr +$filesize && "			\
-	"erase $ubootaddr +$filesize && "			\
-	"cp.b $loadaddr $ubootaddr $filesize && "		\
-	"protect on $ubootaddr +$filesize && "			\
-	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=2000000\0"					\
-	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
-	"fdtaddr=1e00000\0"					\
-	"fdtfile=b4860qds/b4860qds.dtb\0"				\
-	"bdev=sda3\0"
-
-/* For emulation this causes u-boot to jump to the start of the proof point
-   app code automatically */
-#define CONFIG_PROOF_POINTS			\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "cpu 1 release 0x29000000 - - -;"		\
- "cpu 2 release 0x29000000 - - -;"		\
- "cpu 3 release 0x29000000 - - -;"		\
- "cpu 4 release 0x29000000 - - -;"		\
- "cpu 5 release 0x29000000 - - -;"		\
- "cpu 6 release 0x29000000 - - -;"		\
- "cpu 7 release 0x29000000 - - -;"		\
- "go 0x29000000"
-
-#define CONFIG_HVBOOT	\
- "setenv bootargs config-addr=0x60000000; "	\
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU				\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "cpu 1 release 0x01000000 - - -;"		\
- "cpu 2 release 0x01000000 - - -;"		\
- "cpu 3 release 0x01000000 - - -;"		\
- "cpu 4 release 0x01000000 - - -;"		\
- "cpu 5 release 0x01000000 - - -;"		\
- "cpu 6 release 0x01000000 - - -;"		\
- "cpu 7 release 0x01000000 - - -;"		\
- "go 0x01000000"
-
-#define CONFIG_LINUX				\
- "setenv bootargs root=/dev/ram rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "setenv ramdiskaddr 0x02000000;"		\
- "setenv fdtaddr 0x01e00000;"			\
- "setenv loadaddr 0x1000000;"			\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT					\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND			\
-	"setenv bootargs root=/dev/nfs rw "	\
-	"nfsroot=$serverip:$rootpath "		\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"		\
-	"tftp $fdtaddr $fdtfile;"		\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $ramdiskaddr $ramdiskfile;"		\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif	/* __CONFIG_H */
