diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 35a1b29ef8..edccf3698c 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1599,7 +1599,6 @@ source "board/freescale/mpc8572ds/Kconfig"
 source "board/freescale/p1023rdb/Kconfig"
 source "board/freescale/p1_twr/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"
-source "board/freescale/t208xqds/Kconfig"
 source "board/freescale/t208xrdb/Kconfig"
 source "board/freescale/t4qds/Kconfig"
 source "board/freescale/t4rdb/Kconfig"
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
deleted file mode 100644
index 5a435c2695..0000000000
--- a/board/freescale/t208xqds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T2080QDS || TARGET_T2081QDS
-
-config SYS_BOARD
-	default "t208xqds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T208xQDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
deleted file mode 100644
index 790b009c51..0000000000
--- a/board/freescale/t208xqds/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-T208XQDS BOARD
-M:	Shengzhou Liu <Shengzhou.Liu at nxp.com>
-S:	Maintained
-F:	board/freescale/t208xqds/
-F:	include/configs/T208xQDS.h
-F:	configs/T2080QDS_defconfig
-F:	configs/T2080QDS_NAND_defconfig
-F:	configs/T2080QDS_SDCARD_defconfig
-F:	configs/T2080QDS_SPIFLASH_defconfig
-F:	configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
-F:	configs/T2081QDS_defconfig
-F:	configs/T2081QDS_NAND_defconfig
-F:	configs/T2081QDS_SDCARD_defconfig
-F:	configs/T2081QDS_SPIFLASH_defconfig
-F:	configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
-
-T2080QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta at nxp.com>
-S:	Maintained
-F:	configs/T2080QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
deleted file mode 100644
index 587903a623..0000000000
--- a/board/freescale/t208xqds/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_PCI)      += pci.o
-endif
-
-obj-y   += ddr.o
-obj-y   += law.o
-obj-y   += tlb.o
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
deleted file mode 100755
index d690857f2e..0000000000
--- a/board/freescale/t208xqds/README
+++ /dev/null
@@ -1,293 +0,0 @@
-The T2080QDS is a high-performance computing evaluation, development and
-test platform supporting the T2080 QorIQ Power Architecture processor.
-
-T2080 SoC Overview
-------------------
-The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
-Architecture processor cores with high-performance datapath acceleration
-logic and network and peripheral bus interfaces required for networking,
-telecom/datacom, wireless infrastructure, and mil/aerospace applications.
-
-T2080 includes the following functions and features:
- - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- - Hierarchical interconnect fabric
- - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- - 16 SerDes lanes up to 10.3125 GHz
- - 8 Ethernet interfaces, supporting combinations of the following:
-   - Up to four 10 Gbps Ethernet MACs
-   - Up to eight 1 Gbps Ethernet MACs
-   - Up to four 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
-   - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 2.0) controllers
-   - Two high-speed USB 2.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
-   - Enhanced serial peripheral interface (eSPI)
-   - Four I2C controllers
-   - Four 2-pin UARTs or two 4-pin UARTs
-   - Integrated Flash Controller supporting NAND and NOR flash
- - Three eight-channel DMA engines
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ Platform's Trust Architecture 2.0
-
-Differences between T2080 and T2081
------------------------------------
-  Feature		T2080	 T2081
-  1G Ethernet numbers:  8	 6
-  10G Ethernet numbers: 4	 2
-  SerDes lanes:		16	 8
-  Serial RapidIO,RMan:  2	 no
-  SATA Controller:	2	 no
-  Aurora:		yes	 no
-  SoC Package:		896-pins 780-pins
-
-
-T2080QDS feature overview
--------------------------
-Processor:
- - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
-Memory:
- - Single memory controller capable of supporting DDR3 and DDR3-LV devices
- - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
-Ethernet interfaces:
- - Two 1Gbps RGMII on-board ports
- - Four 10Gbps XFI on-board cages
- - 1Gbps/2.5Gbps SGMII Riser card
- - 10Gbps XAUI Riser card
-Accelerator:
- - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
-SerDes:
- - 16 lanes up to 10.3125GHz
- - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
-IFC:
- - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
-eSPI:
- - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
-USB:
- - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
-PCIE:
- - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
-SATA:
- - Two SATA 2.0 ports on-board
-SRIO:
- - Two Serial RapidIO 2.0 ports up to 5 GHz
-eSDHC:
- - Supports SD/SDHC/SDXC/eMMC Card
-I2C:
- - Four I2C controllers.
-UART:
- - Dual 4-pins UART serial ports
-System Logic:
- - QIXIS-II FPGA system controll
-Debug Features:
- - Support Legacy, COP/JTAG, Aurora, Event and EVT
-XFI:
- - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
- a on-board SFP+ cages, which to house optical module (fiber cable) or
- direct attach cable(copper), the copper cable is used to emulate
- 10GBASE-KR scenario.
- So, for XFI usage, there are two scenarios, one will use fiber cable,
- another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
- introduced to indicate a XFI port will use copper cable, and U-Boot
- will fixup the dtb accordingly.
- It's used as: fsl_10gkr_copper:<10g_mac_name>
- The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
- do not have to be coexist in hwconfig. If a MAC is listed in the env
- "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
- will be used by default.
- for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
- hwconfig, then both four XFI ports will use copper cable.
- set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
- XFI ports will use copper cable, the other two XFI ports will use fiber
- cable.
-1000BASE-KX(1G-KX):
- - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
- runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
- in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
- Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
- initialization.
- Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
- 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
- MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
- stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
- For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
- hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
-
-System Memory map
-----------------
-
-Start Address  End Address      Description			Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD			4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
-0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space		64KB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal	32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal	32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
-0xC_4000_0000  0xC_4FFF_FFFF    PCI Express 4 Mem Space		256MB
-0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 3 Mem Space		256MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 2 Mem Space		256MB
-0xC_0000_0000  0xC_1FFF_FFFF    PCI Express 1 Mem Space		512MB
-0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
-
-
-128M NOR Flash memory Map
--------------------------
-Start Address   End Address	Definition			Max size
-0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
-0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
-0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
-0xED300000	0xEFEFFFFF	rootfs (alt bank)		44MB
-0xEC800000	0xEC8FFFFF	Hardware device tree (alt bank)	1MB
-0xEC020000	0xEC7FFFFF	Linux.uImage (alt bank)		7MB + 875KB
-0xEC000000	0xEC01FFFF	RCW (alt bank)			128KB
-0xEBF40000	0xEBFFFFFF	U-Boot (alt bank)		768KB
-0xEBF20000	0xEBF3FFFF	U-Boot env (alt bank)		128KB
-0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
-0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
-0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	1MB
-0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
-0xE8000000	0xE801FFFF	RCW (current bank)		128KB
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
-   a. build NOR boot image
-	$  make T2080QDS_config
-	$  make
-   b. program u-boot.bin image to NOR flash
-	=> tftp 1000000 u-boot.bin
-	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
-	set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
-   Switching between default bank0 and alternate bank4 on NOR flash
-   To change boot source to vbank4:
-	by software:   run command 'qixis_reset altbank' in U-Boot.
-	by DIP-switch: set SW6[1:4] = '0100'
-
-   To change boot source to vbank0:
-	by software:   run command 'qixis_reset' in U-Boot.
-	by DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
-   a. build PBL image for NAND boot
-	$ make T2080QDS_NAND_config
-	$ make
-   b. program u-boot-with-spl-pbl.bin to NAND flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> nand erase 0 $filesize
-	=> nand write 1000000 0 $filesize
-	set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
-   a. build PBL image for SPI boot
-	$ make T2080QDS_SPIFLASH_config
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SPI flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> sf probe 0
-	=> sf erase 0 f0000
-	=> sf write 1000000 0 $filesize
-	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
-   a. build PBL image for SD boot
-	$ make T2080QDS_SDCARD_config
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SD/MMC card
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> mmc write 1000000 8 0x800
-	=> tftp 1000000 fsl_fman_ucode_T2080_xx.bin
-	=> mmc write 1000000 0x820 80
-	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area		   | Address			|
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB)		|
--------------------------------------------------
-|GD, BD		   | 0xFFFC8000 (4KB)		|
--------------------------------------------------
-|ENV		   | 0xFFFC9000 (8KB)		|
--------------------------------------------------
-|HEAP		   | 0xFFFCB000 (50KB)		|
--------------------------------------------------
-|STACK		   | 0xFFFD8000 (22KB)		|
--------------------------------------------------
-|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
--------------------------------------------------
-
-NAND Flash memory Map on T2080QDS
---------------------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot img	1MB  (2 blocks)
-0x100000	0x17FFFF	U-Boot env	512KB (1 block)
-0x180000	0x1FFFFF	FMAN ucode	512KB (1 block)
-
-
-Micro SD Card memory Map on T2080QDS
-----------------------------------------------------
-Block		#blocks		Definition	Size
-0x008		2048		U-Boot img	1MB
-0x800		0016		U-Boot env	8KB
-0x820		0128		FMAN ucode	64KB
-
-
-SPI Flash memory Map on T2080QDS
-----------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot img	1MB
-0x100000	0x101FFF	U-Boot env	8KB
-0x110000	0x11FFFF	FMAN ucode	64KB
-
-
-How to update the ucode of Freescale FMAN
------------------------------------------
-=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
-=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
-
-
-For more details, please refer to T2080QDS User Guide and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
-
-Device tree support and how to enable it for different configs
---------------------------------------------------------------
-Device tree support is available for t2080qds for below mentioned boot,
-1. NOR Boot
-2. NAND Boot
-3. SD Boot
-4. SPIFLASH Boot
-
-To enable device tree support for other boot, below configs need to be
-enabled in relative defconfig file,
-1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
-2. CONFIG_OF_CONTROL
-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
-   CONFIG_RESET_VECTOR_ADDRESS - 0xffc
-
-If device tree support is enabled in defconfig,
-1. use 'u-boot-with-dtb.bin' for NOR boot.
-2. use 'u-boot-with-spl-pbl.bin' for other boot.
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
deleted file mode 100644
index 3317f99c81..0000000000
--- a/board/freescale/t208xqds/ddr.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	/*
-	 * we use identical timing for all slots. If needed, change the code
-	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
-	 */
-	if (popts->registered_dimm_en)
-		pbsp = rdimms[0];
-	else
-		pbsp = udimms[0];
-
-	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x64;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	puts("Initializing....using SPD\n");
-	dram_size = fsl_ddr_sdram();
-#else
-	/* DDR has been initialised by first stage boot loader */
-	dram_size =  fsl_ddr_sdram_size();
-#endif
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
deleted file mode 100644
index 9dd39813bf..0000000000
--- a/board/freescale/t208xqds/ddr.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
-	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
-	 */
-	{2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
-	{2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
-	{2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
-	{2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
-	{2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
-	{1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
-	{1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
-	{1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
-	{1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
-	{1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
-	{}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-	/* TODO: need tuning these parameters if RDIMM is used */
-	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-#endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
deleted file mode 100644
index 938e606641..0000000000
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ /dev/null
@@ -1,826 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- *
- * Shengzhou Liu <Shengzhou.Liu at freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <log.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-#include "../common/qixis.h"
-#include "../common/fman.h"
-#include "t208xqds_qixis.h"
-#include <linux/libfdt.h>
-
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII1	0
-#define EMI1_RGMII2     1
-#define EMI1_SLOT1	2
-#if defined(CONFIG_TARGET_T2080QDS)
-#define EMI1_SLOT2	6
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI2            7
-#elif defined(CONFIG_TARGET_T2081QDS)
-#define EMI1_SLOT2      3
-#define EMI1_SLOT3      4
-#define EMI1_SLOT5      5
-#define EMI1_SLOT6      6
-#define EMI1_SLOT7      7
-#define EMI2		8
-#endif
-
-#define PCCR1_SGMIIA_KX_MASK		0x00008000
-#define PCCR1_SGMIIB_KX_MASK		0x00004000
-#define PCCR1_SGMIIC_KX_MASK		0x00002000
-#define PCCR1_SGMIID_KX_MASK		0x00001000
-#define PCCR1_SGMIIE_KX_MASK		0x00000800
-#define PCCR1_SGMIIF_KX_MASK		0x00000400
-#define PCCR1_SGMIIG_KX_MASK		0x00000200
-#define PCCR1_SGMIIH_KX_MASK		0x00000100
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-#if defined(CONFIG_TARGET_T2080QDS)
-	"T2080QDS_MDIO_RGMII1",
-	"T2080QDS_MDIO_RGMII2",
-	"T2080QDS_MDIO_SLOT1",
-	"T2080QDS_MDIO_SLOT3",
-	"T2080QDS_MDIO_SLOT4",
-	"T2080QDS_MDIO_SLOT5",
-	"T2080QDS_MDIO_SLOT2",
-	"T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_TARGET_T2081QDS)
-	"T2081QDS_MDIO_RGMII1",
-	"T2081QDS_MDIO_RGMII2",
-	"T2081QDS_MDIO_SLOT1",
-	"T2081QDS_MDIO_SLOT2",
-	"T2081QDS_MDIO_SLOT3",
-	"T2081QDS_MDIO_SLOT5",
-	"T2081QDS_MDIO_SLOT6",
-	"T2081QDS_MDIO_SLOT7",
-	"T2081QDS_MDIO_10GC",
-#endif
-};
-
-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_TARGET_T2080QDS)
-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_TARGET_T2081QDS)
-static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
-#endif
-
-static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = t208xqds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct t208xqds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void t208xqds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if (muxval < 8) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	t208xqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	t208xqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t208xqds_mdio_reset(struct mii_dev *bus)
-{
-	struct t208xqds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t208xqds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t208xqds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate t208xqds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate t208xqds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t208xqds_mdio_read;
-	bus->write = t208xqds_mdio_write;
-	bus->reset = t208xqds_mdio_reset;
-	strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-				enum fm_port port, int offset)
-{
-	int phy;
-	char alias[20];
-	char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
-	char buf[32] = "serdes-1,";
-	struct fixed_link f_link;
-	int media_type = 0;
-	const char *phyconn;
-	int off;
-
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_TARGET_T2080QDS
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
-#endif
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
-		phy = fm_info_get_phy_address(port);
-		switch (port) {
-#if defined(CONFIG_TARGET_T2080QDS)
-		case FM1_DTSEC1:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx1");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
-				sprintf(buf, "%s%s%s", buf, "lane-c,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIH_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC2:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx2");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
-				sprintf(buf, "%s%s%s", buf, "lane-d,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIG_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC9:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx9");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
-				sprintf(buf, "%s%s%s", buf, "lane-a,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIE_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC10:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx10");
-				fdt_status_okay_by_alias(fdt,
-							 "1gkx_pcs_mdio10");
-				sprintf(buf, "%s%s%s", buf, "lane-b,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIF_KX_MASK);
-				break;
-			}
-			if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			} else if (mdio_mux[port] == EMI1_SLOT3) {
-				sprintf(alias, "phy_sgmii_s3_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-			}
-			break;
-		case FM1_DTSEC5:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx5");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
-				sprintf(buf, "%s%s%s", buf, "lane-g,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIIC_KX_MASK);
-				break;
-			}
-		case FM1_DTSEC6:
-			if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						   "phy_1gkx6");
-				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
-				sprintf(buf, "%s%s%s", buf, "lane-h,",
-						(char *)lane_mode[0]);
-				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
-					 PCCR1_SGMIID_KX_MASK);
-				break;
-			}
-			if (mdio_mux[port] == EMI1_SLOT1) {
-				sprintf(alias, "phy_sgmii_s1_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot1");
-			} else if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			}
-			break;
-#elif defined(CONFIG_TARGET_T2081QDS)
-		case FM1_DTSEC1:
-		case FM1_DTSEC2:
-		case FM1_DTSEC5:
-		case FM1_DTSEC6:
-		case FM1_DTSEC9:
-		case FM1_DTSEC10:
-			if (mdio_mux[port] == EMI1_SLOT2) {
-				sprintf(alias, "phy_sgmii_s2_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-			} else if (mdio_mux[port] == EMI1_SLOT3) {
-				sprintf(alias, "phy_sgmii_s3_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-			} else if (mdio_mux[port] == EMI1_SLOT5) {
-				sprintf(alias, "phy_sgmii_s5_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot5");
-			} else if (mdio_mux[port] == EMI1_SLOT6) {
-				sprintf(alias, "phy_sgmii_s6_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot6");
-			} else if (mdio_mux[port] == EMI1_SLOT7) {
-				sprintf(alias, "phy_sgmii_s7_%x", phy);
-				fdt_set_phy_handle(fdt, compat, addr, alias);
-				fdt_status_okay_by_alias(fdt, "emi1_slot7");
-			}
-			break;
-#endif
-		default:
-			break;
-		}
-		if (media_type) {
-			/* set property for 1000BASE-KX in dtb */
-			off = fdt_node_offset_by_compat_reg(fdt,
-					"fsl,fman-memac-mdio", addr + 0x1000);
-			fdt_setprop_string(fdt, off, "lane-instance", buf);
-		}
-
-	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
-		switch (srds_s1) {
-		case 0x66: /* XFI interface */
-		case 0x6b:
-		case 0x6c:
-		case 0x6d:
-		case 0x71:
-			/*
-			* if the 10G is XFI, check hwconfig to see what is the
-			* media type, there are two types, fiber or copper,
-			* fix the dtb accordingly.
-			*/
-			switch (port) {
-			case FM1_10GEC1:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
-				/* it's MAC9 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi9");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
-				sprintf(buf, "%s%s%s", buf, "lane-a,",
-						(char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC2:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
-				/* it's MAC10 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi10");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
-				sprintf(buf, "%s%s%s", buf, "lane-b,",
-						(char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC3:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
-				/* it's MAC1 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi1");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
-				sprintf(buf, "%s%s%s", buf, "lane-c,",
-						(char *)lane_mode[1]);
-			}
-				break;
-			case FM1_10GEC4:
-			if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
-				/* it's MAC2 */
-				media_type = 1;
-				fdt_set_phy_handle(fdt, compat, addr,
-						"phy_xfi2");
-				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
-				sprintf(buf, "%s%s%s", buf, "lane-d,",
-						(char *)lane_mode[1]);
-			}
-				break;
-			default:
-				return;
-			}
-
-			if (!media_type) {
-				phyconn = fdt_getprop(fdt, offset,
-						      "phy-connection-type",
-						      NULL);
-				if (is_backplane_mode(phyconn)) {
-					/* Backplane KR mode: skip fixups */
-					printf("Interface %d in backplane KR mode\n",
-					       port);
-				} else {
-					/* fixed-link for XFI fiber cable */
-					f_link.phy_id = port;
-					f_link.duplex = 1;
-					f_link.link_speed = 10000;
-					f_link.pause = 0;
-					f_link.asym_pause = 0;
-					fdt_delprop(fdt, offset, "phy-handle");
-					fdt_setprop(fdt, offset, "fixed-link",
-						    &f_link, sizeof(f_link));
-				}
-			} else {
-				/* set property for copper cable */
-				off = fdt_node_offset_by_compat_reg(fdt,
-					"fsl,fman-memac-mdio", addr + 0x1000);
-				fdt_setprop_string(fdt, off,
-					"lane-instance", buf);
-			}
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	return;
-}
-
-/*
- * This function reads RCW to check if Serdes1{A:H} is configured
- * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	switch (srds_s1) {
-#if defined(CONFIG_TARGET_T2080QDS)
-	case 0x51:
-	case 0x5f:
-	case 0x65:
-	case 0x6b:
-	case 0x71:
-		lane_to_slot[5] = 2;
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-	case 0xd3:
-	case 0xd9:
-	case 0xcb:
-		lane_to_slot[6] = 2;
-		lane_to_slot[7] = 2;
-		break;
-	case 0xda:
-		lane_to_slot[4] = 3;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-#elif defined(CONFIG_TARGET_T2081QDS)
-	case 0x6b:
-		lane_to_slot[4] = 1;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xca:
-	case 0xcb:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xf2:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[5] = 4;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 7;
-		break;
-#endif
-	default:
-		break;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot, interface;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
-	u32 srds_s1;
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_TARGET_T2080QDS)
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-#endif
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_TARGET_T2081QDS)
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
-	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-#endif
-	t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
-			FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
-		fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-	else
-		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
-
-	switch (srds_s1) {
-	case 0x1b:
-	case 0x1c:
-	case 0x95:
-	case 0xa2:
-	case 0x94:
-		/* T2080QDS: SGMII in Slot3;  T2081QDS: SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: SGMII in Slot1 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x50:
-	case 0x51:
-	case 0x5e:
-	case 0x5f:
-	case 0x64:
-	case 0x65:
-		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
-		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x66:
-	case 0x67:
-		/*
-		 * XFI does not need a PHY to work, but to avoid U-Boot use
-		 * default PHY address which is zero to a MAC when it found
-		 * a MAC has no PHY address, we give a PHY address to XFI
-		 * MAC, and should not use a real XAUI PHY address, since
-		 * MDIO can access it successfully, and then MDIO thinks
-		 * the XAUI card is used for the XFI MAC, which will cause
-		 * error.
-		 */
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		break;
-	case 0x6a:
-	case 0x6b:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		fm_info_set_phy_address(FM1_10GEC3, 6);
-		fm_info_set_phy_address(FM1_10GEC4, 7);
-		/* T2080QDS: SGMII in Slot2;  T2081QDS: in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0x6c:
-	case 0x6d:
-		fm_info_set_phy_address(FM1_10GEC1, 4);
-		fm_info_set_phy_address(FM1_10GEC2, 5);
-		/* T2080QDS: SGMII in Slot3;  T2081QDS: in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	case 0x70:
-	case 0x71:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa6:
-	case 0x8e:
-	case 0x8f:
-	case 0x82:
-	case 0x83:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0xa4:
-	case 0x96:
-	case 0x8a:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-#if defined(CONFIG_TARGET_T2080QDS)
-	case 0xd9:
-	case 0xd3:
-	case 0xcb:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-		/* SGMII in Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-#elif defined(CONFIG_TARGET_T2081QDS)
-	case 0xca:
-	case 0xcb:
-		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		/* SGMII in Slot5 */
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
-		/* SGMII in Slot6 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		/* SGMII in Slot7 */
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
-		break;
-#endif
-	case 0xf2:
-		/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	default:
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		interface = fm_info_get_enet_if(i);
-		switch (interface) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			debug("FM1 at DTSEC%u expects SGMII in slot %u\n",
-			      idx + 1, slot);
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-#if defined(CONFIG_TARGET_T2081QDS)
-			case 5:
-				mdio_mux[i] = EMI1_SLOT5;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 6:
-				mdio_mux[i] = EMI1_SLOT6;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-			case 7:
-				mdio_mux[i] = EMI1_SLOT7;
-				fm_info_set_mdio(i, mii_dev_for_muxval(
-						 mdio_mux[i]));
-				break;
-#endif
-			}
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC3)
-				mdio_mux[i] = EMI1_RGMII1;
-			else if (i == FM1_DTSEC4 || FM1_DTSEC10)
-				mdio_mux[i] = EMI1_RGMII2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-			break;
-		default:
-			break;
-		}
-	}
-
-	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
-		idx = i - FM1_10GEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_XGMII:
-			if (srds_s1 == 0x51) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						XAUI_FM1_MAC9 + idx);
-			} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
-				lane = serdes_get_first_lane(FSL_SRDS_1,
-						HIGIG_FM1_MAC9 + idx);
-			} else {
-				if (i == FM1_10GEC1 || i == FM1_10GEC2)
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC9 + idx);
-				else
-					lane = serdes_get_first_lane(FSL_SRDS_1,
-						XFI_FM1_MAC1 + idx);
-			}
-
-			if (lane < 0)
-				break;
-			mdio_mux[i] = EMI2;
-			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-
-			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
-			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
-			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
-			    (srds_s1 == 0x71)) {
-				/* As XFI is in cage intead of a slot, so
-				 * ensure doesn't disable the corresponding port
-				 */
-				break;
-			}
-
-			slot = lane_to_slot[lane];
-			if (QIXIS_READ(present2) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			break;
-		default:
-			break;
-		}
-	}
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
deleted file mode 100644
index 40fdcf61c0..0000000000
--- a/board/freescale/t208xqds/law.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	/* Limit DCSR to 32M to access NPC Trace Buffer */
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
deleted file mode 100644
index e335592776..0000000000
--- a/board/freescale/t208xqds/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
deleted file mode 100644
index 40eb5d30a6..0000000000
--- a/board/freescale/t208xqds/spl.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-#include "../common/qixis.h"
-#include "t208xqds_qixis.h"
-#include "../common/spl.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, ccb_clk;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	ccb_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     ccb_clk / 16 / CONFIG_BAUDRATE);
-
-#if defined(CONFIG_SPL_MMC_BOOT)
-	puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	puts("\nSPI boot...\n");
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	puts("\nNAND boot...\n");
-#endif
-
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	arch_cpu_init();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)SPL_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
-	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			       (uchar *)SPL_ENV_ADDR);
-#endif
-
-	gd->env_addr  = (ulong)(SPL_ENV_ADDR);
-	gd->env_valid = ENV_VALID;
-
-	i2c_init_all();
-
-	dram_init();
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	fsl_spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/board/freescale/t208xqds/t2080_nand_rcw.cfg b/board/freescale/t208xqds/t2080_nand_rcw.cfg
deleted file mode 100644
index 52a1652a22..0000000000
--- a/board/freescale/t208xqds/t2080_nand_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 e8104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_sd_rcw.cfg b/board/freescale/t208xqds/t2080_sd_rcw.cfg
deleted file mode 100644
index 73f53faa25..0000000000
--- a/board/freescale/t208xqds/t2080_sd_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 68104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_spi_rcw.cfg b/board/freescale/t208xqds/t2080_spi_rcw.cfg
deleted file mode 100644
index 8474c8ef7c..0000000000
--- a/board/freescale/t208xqds/t2080_spi_rcw.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-
-#For T2080 v1.0
-#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
-#12100017 15000000 00000000 00000000
-#66150002 00008400 e8104000 c1000000
-#00000000 00000000 00000000 000307fc
-#00000000 00000000 00000000 00000004
-
-#For T2080 v1.1
-#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
-0c070012 0e000000 00000000 00000000
-66150002 00000000 58104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_nand_rcw.cfg b/board/freescale/t208xqds/t2081_nand_rcw.cfg
deleted file mode 100644
index a2d5ecf4ad..0000000000
--- a/board/freescale/t208xqds/t2081_nand_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 e8104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_sd_rcw.cfg b/board/freescale/t208xqds/t2081_sd_rcw.cfg
deleted file mode 100644
index daced6796b..0000000000
--- a/board/freescale/t208xqds/t2081_sd_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 68104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_spi_rcw.cfg b/board/freescale/t208xqds/t2081_spi_rcw.cfg
deleted file mode 100644
index 79ba1f1ab7..0000000000
--- a/board/freescale/t208xqds/t2081_spi_rcw.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#Default SerDes Protocol: 0x6C
-#Core/DDR: 1533Mhz/2133MT/s
-12100017 15000000 00000000 00000000
-6c000002 00008000 58104000 c1000000
-00000000 00000000 00000000 000307fc
-00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
deleted file mode 100644
index 43be8a864e..0000000000
--- a/board/freescale/t208xqds/t208x_pbi.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-# Refer doc/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
-094fc030 00008148
-094fd030 00008148
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
deleted file mode 100644
index 4979085e19..0000000000
--- a/board/freescale/t208xqds/t208xqds.c
+++ /dev/null
@@ -1,489 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/qixis.h"
-#include "../common/vsc3316_3308.h"
-#include "../common/vid.h"
-#include "t208xqds.h"
-#include "t208xqds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *freq[4] = {
-		"100.00MHZ(from 8T49N222A)", "125.00MHz",
-		"156.25MHZ", "100.00MHz"
-	};
-
-	printf("Board: %sQDS, ", cpu->name);
-	sw = QIXIS_READ(arch);
-	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
-	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-#ifdef CONFIG_SDCARD
-	puts("SD/MMC\n");
-#elif CONFIG_SPIFLASH
-	puts("SPI\n");
-#else
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank%d\n", sw);
-	else if (sw == 0x8)
-		puts("Promjet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-#endif
-
-	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
-	       qixis_read_tag(buf), (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	puts("SERDES Reference Clocks:\n");
-	sw = QIXIS_READ(brdcfg[2]);
-	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
-	       freq[(sw >> 4) & 0x3]);
-	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
-	       freq[sw & 0x3]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
-	int ret;
-
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-	ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-int i2c_multiplexer_select_vid_channel(u8 channel)
-{
-	return select_i2c_ch_pca9547(channel, 0);
-}
-
-int brd_mux_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 srds_prtcl_s1;
-
-	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
-	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_TARGET_T2080QDS)
-	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
-	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-#endif
-
-	switch (srds_prtcl_s1) {
-	case 0:
-		/* SerDes1 is not enabled */
-		break;
-#if defined(CONFIG_TARGET_T2080QDS)
-	case 0x1b:
-	case 0x1c:
-	case 0xa2:
-		/* SD1(A:D) => SLOT3 SGMII
-		 * SD1(G:H) => SLOT1 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x1a);
-		break;
-	case 0x94:
-	case 0x95:
-		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
-		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
-		 * SD1(E:H) => SLOT1 SGMII at 1.25bps
-		 */
-	case 0x96:
-		/* SD1(A:B) => SLOT3 SGMII at 1.25bps
-		 * SD1(C)   => SFP Module, SGMII at 3.125bps
-		 * SD1(D)   => SFP Module, SGMII at 1.25bps
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x3a);
-		break;
-	case 0x50:
-	case 0x51:
-		/* SD1(A:D) => SLOT3 XAUI
-		 * SD1(E)   => SLOT1 PCIe4
-		 * SD1(F:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x15);
-		break;
-	case 0x66:
-	case 0x67:
-		/* SD1(A:D) => XFI cage
-		 * SD1(E:H) => SLOT1 PCIe4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xfe);
-		break;
-	case 0x6a:
-	case 0x6b:
-		/* SD1(A:D) => XFI cage
-		 * SD1(E)   => SLOT1 PCIe4
-		 * SD1(F:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xf1);
-		break;
-	case 0x6c:
-	case 0x6d:
-		/* SD1(A:B) => XFI cage
-		 * SD1(C:D) => SLOT3 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xda);
-		break;
-	case 0x6e:
-		/* SD1(A:B) => SFP Module, XFI
-		 * SD1(C:D) => SLOT3 SGMII
-		 * SD1(E:F) => SLOT1 PCIe4 x2
-		 * SD1(G:H) => SLOT2 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xd9);
-		break;
-	case 0xda:
-		/* SD1(A:H) => SLOT3 PCIe3 x8
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x0);
-		 break;
-	case 0xc8:
-		/* SD1(A)   => SLOT3 PCIe3 x1
-		 * SD1(B)   => SFP Module, SGMII at 1.25bps
-		 * SD1(C:D) => SFP Module, SGMII at 3.125bps
-		 * SD1(E:F) => SLOT1 PCIe4 x2
-		 * SD1(G:H) => SLOT2 SGMII
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x79);
-		 break;
-	case 0xab:
-		/* SD1(A:D) => SLOT3 PCIe3 x4
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		 QIXIS_WRITE(brdcfg[12], 0x1a);
-		 break;
-#elif defined(CONFIG_TARGET_T2081QDS)
-	case 0x50:
-	case 0x51:
-		/* SD1(A:D) => SLOT2 XAUI
-		 * SD1(E)   => SLOT1 PCIe4 x1
-		 * SD1(F:H) => SLOT3 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x98);
-		QIXIS_WRITE(brdcfg[13], 0x70);
-		break;
-	case 0x6a:
-	case 0x6b:
-		/* SD1(A:D) => XFI SFP Module
-		 * SD1(E)   => SLOT1 PCIe4 x1
-		 * SD1(F:H) => SLOT3 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x80);
-		QIXIS_WRITE(brdcfg[13], 0x70);
-		break;
-	case 0x6c:
-	case 0x6d:
-		/* SD1(A:B) => XFI SFP Module
-		 * SD1(C:D) => SLOT2 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xe8);
-		QIXIS_WRITE(brdcfg[13], 0x0);
-		break;
-	case 0xaa:
-	case 0xab:
-		/* SD1(A:D) => SLOT2 PCIe3 x4
-		 * SD1(F:H) => SLOT1 SGMI4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xf8);
-		QIXIS_WRITE(brdcfg[13], 0x0);
-		break;
-	case 0xca:
-	case 0xcb:
-		/* SD1(A)   => SLOT2 PCIe3 x1
-		 * SD1(B)   => SLOT7 SGMII
-		 * SD1(C)   => SLOT6 SGMII
-		 * SD1(D)   => SLOT5 SGMII
-		 * SD1(E)   => SLOT1 PCIe4 x1
-		 * SD1(F:H) => SLOT3 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x80);
-		QIXIS_WRITE(brdcfg[13], 0x70);
-		break;
-	case 0xde:
-	case 0xdf:
-		/* SD1(A:D) => SLOT2 PCIe3 x4
-		 * SD1(E)   => SLOT1 PCIe4 x1
-		 * SD1(F)   => SLOT4 PCIe1 x1
-		 * SD1(G)   => SLOT3 PCIe2 x1
-		 * SD1(H)   => SLOT7 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x98);
-		QIXIS_WRITE(brdcfg[13], 0x25);
-		break;
-	case 0xf2:
-		/* SD1(A)   => SLOT2 PCIe3 x1
-		 * SD1(B:D) => SLOT7 SGMII
-		 * SD1(E)   => SLOT1 PCIe4 x1
-		 * SD1(F)   => SLOT4 PCIe1 x1
-		 * SD1(G)   => SLOT3 PCIe2 x1
-		 * SD1(H)   => SLOT7 SGMII
-		 */
-		QIXIS_WRITE(brdcfg[12], 0x81);
-		QIXIS_WRITE(brdcfg[13], 0xa5);
-		break;
-#endif
-	default:
-		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
-		       srds_prtcl_s1);
-		return -1;
-	}
-
-#ifdef CONFIG_TARGET_T2080QDS
-	switch (srds_prtcl_s2) {
-	case 0:
-		/* SerDes2 is not enabled */
-		break;
-	case 0x01:
-	case 0x02:
-		/* SD2(A:H) => SLOT4 PCIe1 */
-		QIXIS_WRITE(brdcfg[13], 0x10);
-		break;
-	case 0x15:
-	case 0x16:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:F) => SLOT5 PCIe2
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xb0);
-		break;
-	case 0x18:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:F) => SLOT5 Aurora
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0x78);
-		break;
-	case 0x1f:
-		/*
-		 * SD2(A:D) => SLOT4 PCIe1
-		 * SD2(E:H) => SLOT5 PCIe2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xa0);
-		break;
-	case 0x29:
-	case 0x2d:
-	case 0x2e:
-		/*
-		 * SD2(A:D) => SLOT4 SRIO2
-		 * SD2(E:H) => SLOT5 SRIO1
-		 */
-		QIXIS_WRITE(brdcfg[13], 0xa0);
-		break;
-	case 0x36:
-		/*
-		 * SD2(A:D) => SLOT4 SRIO2
-		 * SD2(E:F) => Aurora
-		 * SD2(G:H) => SATA1,SATA2
-		 */
-		QIXIS_WRITE(brdcfg[13], 0x78);
-		break;
-	default:
-		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
-		       srds_prtcl_s2);
-		return -1;
-	}
-#endif
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	/* Disable remote I2C connection to qixis fpga */
-	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
-
-	/*
-	 * Adjust core voltage according to voltage ID
-	 * This function changes I2C mux to channel 2.
-	 */
-	if (adjust_vdd(0))
-		printf("Warning: Adjusting core voltage failed.\n");
-
-	brd_mux_lane_to_slot();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("SYS Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: SYS clock measurement is invalid, ");
-		printf("using value from brdcfg1.\n");
-	}
-#endif
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
-	/* use accurate clock measurement */
-	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
-	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
-	u32 val;
-
-	val =  freq * base;
-	if (val) {
-		debug("DDR Clock measurement is: %d\n", val);
-		return val;
-	} else {
-		printf("Warning: DDR clock measurement is invalid, ");
-		printf("using value from brdcfg1.\n");
-	}
-#endif
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h
deleted file mode 100644
index 68c758f723..0000000000
--- a/board/freescale/t208xqds/t208xqds.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CORENET_DS_H__
-#define __CORENET_DS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
deleted file mode 100644
index 0f9a45a6fd..0000000000
--- a/board/freescale/t208xqds/t208xqds_qixis.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T208xQDS_QIXIS_H__
-#define __T208xQDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T208xQDS */
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK             0xE0
-#define BRDCFG4_EMISEL_SHIFT            5
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66                 0x0
-#define QIXIS_SYSCLK_83                 0x1
-#define QIXIS_SYSCLK_100                0x2
-#define QIXIS_SYSCLK_125                0x3
-#define QIXIS_SYSCLK_133                0x4
-#define QIXIS_SYSCLK_150                0x5
-#define QIXIS_SYSCLK_160                0x6
-#define QIXIS_SYSCLK_166                0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66                 0x0
-#define QIXIS_DDRCLK_100                0x1
-#define QIXIS_DDRCLK_125                0x2
-#define QIXIS_DDRCLK_133                0x3
-
-#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
-
-#define BRDCFG9_SFP_TX_EN		0x10
-
-#define BRDCFG12_SD3EN_MASK             0x20
-#define BRDCFG12_SD3MX_MASK             0x08
-#define BRDCFG12_SD3MX_SLOT5            0x08
-#define BRDCFG12_SD3MX_SLOT6            0x00
-#define BRDCFG12_SD4EN_MASK             0x04
-#define BRDCFG12_SD4MX_MASK             0x03
-#define BRDCFG12_SD4MX_SLOT7            0x02
-#define BRDCFG12_SD4MX_SLOT8            0x01
-#define BRDCFG12_SD4MX_AURO_SATA        0x00
-#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
deleted file mode 100644
index 1e501da363..0000000000
--- a/board/freescale/t208xqds/tlb.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2013 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
-	 * space is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCIe 1, 0x80000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_512M, 1),
-
-	/* *I*G* - PCIe 2, 0xa0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCIe 3, 0xb0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-
-	/* *I*G* - PCIe 4, 0xc0000000 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 9, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 11, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-	/*
-	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
-	 * fetching ucode and ENV from master
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
-		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
-		      0, 18, BOOKE_PAGESZ_1M, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-		      0, 19, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
deleted file mode 100644
index 52255ed120..0000000000
--- a/configs/T2080QDS_NAND_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
deleted file mode 100644
index ba57ea33b1..0000000000
--- a/configs/T2080QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
deleted file mode 100644
index 9b3f709c87..0000000000
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
deleted file mode 100644
index 5aa45f5a89..0000000000
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 4958435ef4..0000000000
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
deleted file mode 100644
index 602bf577e0..0000000000
--- a/configs/T2080QDS_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080QDS=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
deleted file mode 100644
index 85381c60ef..0000000000
--- a/configs/T2081QDS_NAND_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
deleted file mode 100644
index bbc8b7666e..0000000000
--- a/configs/T2081QDS_SDCARD_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
deleted file mode 100644
index b02505be21..0000000000
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC9000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index a10f39b336..0000000000
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
deleted file mode 100644
index 22ca08363c..0000000000
--- a/configs/T2081QDS_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2081QDS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
deleted file mode 100644
index c54f7f53e5..0000000000
--- a/include/configs/T208xQDS.h
+++ /dev/null
@@ -1,771 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T2080/T2081 QDS board configuration file
- */
-
-#ifndef __T208xQDS_H
-#define __T208xQDS_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1		/* SRIO port 1 */
-#define CONFIG_SRIO2		/* SRIO port 2 */
-#elif defined(CONFIG_ARCH_T2081)
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_ENV_OVERWRITE
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
-
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO		0x40000
-#define CONFIG_SPL_MAX_SIZE		0x28000
-#define RESET_VECTOR_OFFSET		0x27FFC
-#define BOOT_PAGE_OFFSET		0x27000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
-#endif
-#endif
-
-#ifdef CONFIG_SDCARD
-#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
-#endif
-#endif
-
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB		/* toggle branch predition */
-#define CONFIG_DDR_ECC
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
-
-#if defined(CONFIG_SPIFLASH)
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_SYS_MMC_ENV_DEV	0
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
-#define CONFIG_SYS_L3_SIZE		(512 << 10)
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR	0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM	0
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
-#define SPD_EEPROM_ADDRESS1	0x51
-#define SPD_EEPROM_ADDRESS2	0x52
-#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-#define CTRL_INTLV_PREFERED	cacheline
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
-				+ 0x8000000) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
-				CSPR_PORT_SIZE_16 | \
-				CSPR_MSEL_NOR | \
-				CSPR_V)
-#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
-				FTIM0_NOR_TEADC(0x5) | \
-				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
-				FTIM1_NOR_TRAD_NOR(0x1A) |\
-				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
-				FTIM2_NOR_TCH(0x4) | \
-				FTIM2_NOR_TWPH(0x0E) | \
-				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
-					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
-#define QIXIS_BASE			0xffdf0000
-#define QIXIS_LBMAP_SWITCH		6
-#define QIXIS_LBMAP_MASK		0x0f
-#define QIXIS_LBMAP_SHIFT		0
-#define QIXIS_LBMAP_DFLTBANK		0x00
-#define QIXIS_LBMAP_ALTBANK		0x04
-#define QIXIS_LBMAP_NAND		0x09
-#define QIXIS_LBMAP_SD			0x00
-#define QIXIS_RCW_SRC_NAND		0x104
-#define QIXIS_RCW_SRC_SD		0x040
-#define QIXIS_RST_CTL_RESET		0x83
-#define QIXIS_RST_FORCE_MEM		0x1
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
-
-#define CONFIG_SYS_CSPR3_EXT	(0xf)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 \
-				| CSPR_MSEL_GPCM \
-				| CSPR_V)
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3	0x0
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
-					FTIM0_GPCM_TEADC(0x0e) | \
-					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
-					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x8) | \
-					FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3		0x0
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_BASE		0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
-				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
-				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
-				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
-				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
-				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
-					FTIM0_NAND_TWP(0x18)    | \
-					FTIM0_NAND_TWCHT(0x07)  | \
-					FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)   | \
-					FTIM1_NAND_TRR(0x0e)    | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
-					FTIM2_NAND_TREH(0x0a)   | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW		11
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/*
- * I2C
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
-#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
-#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
-#define CONFIG_SYS_FSL_I2C_SPEED   100000
-#define CONFIG_SYS_FSL_I2C2_SPEED  100000
-#define CONFIG_SYS_FSL_I2C3_SPEED  100000
-#define CONFIG_SYS_FSL_I2C4_SPEED  100000
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-
-#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
-#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
-#define I2C_MUX_CH_DEFAULT	0x8
-
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR           0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
-
-#define CONFIG_VID_FLS_ENV		"t208xqds_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T208xQDS */
-#define VDD_MV_MIN			819
-#define VDD_MV_MAX			1212
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#endif
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS	18
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
-					CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS	18
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
-					CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
-/*
- * Slave has no ucode locally, it can fetch this from remote. When implementing
- * in two corenet boards, slave's ucode could be stored in master's memory
- * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO or PCIE outbound window->master inbound window->
- * master LAW->the ucode address in master's memory space.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define RGMII_PHY1_ADDR	0x1
-#define RGMII_PHY2_ADDR	0x2
-#define FM1_10GEC1_PHY_ADDR	  0x3
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME		"FM1 at DTSEC3"
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
-#define CONFIG_LBA48
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-/*
- * SDHC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
-#endif
-
-/*
- * Dynamic MTD Partition support with mtdparts
- */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH	 "/opt/nfsroot"
-#define CONFIG_BOOTFILE	 "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-#define __USB_PHY_TYPE		utmi
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"hwconfig=fsl_ddr:"					\
-	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
-	"bank_intlv=auto;"					\
-	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
-	"tftpflash=tftpboot $loadaddr $uboot && "		\
-	"protect off $ubootaddr +$filesize && "			\
-	"erase $ubootaddr +$filesize && "			\
-	"cp.b $loadaddr $ubootaddr $filesize && "		\
-	"protect on $ubootaddr +$filesize && "			\
-	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=2000000\0"					\
-	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
-	"fdtaddr=1e00000\0"					\
-	"fdtfile=t2080qds/t2080qds.dtb\0"			\
-	"bdev=sda3\0"
-
-/*
- * For emulation this causes u-boot to jump to the start of the
- * proof point app code automatically
- */
-#define CONFIG_PROOF_POINTS				\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"cpu 1 release 0x29000000 - - -;"		\
-	"cpu 2 release 0x29000000 - - -;"		\
-	"cpu 3 release 0x29000000 - - -;"		\
-	"cpu 4 release 0x29000000 - - -;"		\
-	"cpu 5 release 0x29000000 - - -;"		\
-	"cpu 6 release 0x29000000 - - -;"		\
-	"cpu 7 release 0x29000000 - - -;"		\
-	"go 0x29000000"
-
-#define CONFIG_HVBOOT				\
-	"setenv bootargs config-addr=0x60000000; "	\
-	"bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_ALU				\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"cpu 1 release 0x01000000 - - -;"		\
-	"cpu 2 release 0x01000000 - - -;"		\
-	"cpu 3 release 0x01000000 - - -;"		\
-	"cpu 4 release 0x01000000 - - -;"		\
-	"cpu 5 release 0x01000000 - - -;"		\
-	"cpu 6 release 0x01000000 - - -;"		\
-	"cpu 7 release 0x01000000 - - -;"		\
-	"go 0x01000000"
-
-#define CONFIG_LINUX				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"setenv ramdiskaddr 0x02000000;"		\
-	"setenv fdtaddr 0x00c00000;"			\
-	"setenv loadaddr 0x1000000;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT					\
-	"setenv bootargs root=/dev/$bdev rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND			\
-	"setenv bootargs root=/dev/nfs rw "	\
-	"nfsroot=$serverip:$rootpath "		\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $loadaddr $bootfile;"		\
-	"tftp $fdtaddr $fdtfile;"		\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND				\
-	"setenv bootargs root=/dev/ram rw "		\
-	"console=$consoledev,$baudrate $othbootargs;"	\
-	"tftp $ramdiskaddr $ramdiskfile;"		\
-	"tftp $loadaddr $bootfile;"			\
-	"tftp $fdtaddr $fdtfile;"			\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif	/* __T208xQDS_H */
