[v12,15/21] riscv: Add option to support RISC-V privileged spec 1.9

Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson <seanga2 at gmail.com>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v6:
- Reformat so chechpatch errors less

Changes in v5:
- Rename to 1.9 to reflect the spec as implemented by the k210

Changes in v4:
- Fixed CSRs not being defined properly (thanks bmeng)
- Added ifdefs for all changed CSRs (e.g. for VM)
- Also properly disable VM on boot

Changes in v3:
- Renamed from "riscv: Add option to disable writes to mcounteren"
- Added original functionality back for older priv specs.

Changes in v2:
- Moved forward in the patch series

 arch/riscv/Kconfig           | 10 +++++++++
 arch/riscv/cpu/cpu.c         |  9 ++++++++
 arch/riscv/include/asm/csr.h | 40 ++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)

Message ID	20200520191738.337845-16-seanga2@gmail.com
State	Superseded
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: seanga2 at gmail.com (Sean Anderson) Date: Wed, 20 May 2020 15:17:32 -0400 Subject: [PATCH v12 15/21] riscv: Add option to support RISC-V privileged spec 1.9 In-Reply-To: <20200520191738.337845-1-seanga2@gmail.com> References: <20200520191738.337845-1-seanga2@gmail.com> Message-ID: <20200520191738.337845-16-seanga2@gmail.com>
Series	riscv: Add Sipeed Maix support \| expand [v12,00/21] riscv: Add Sipeed Maix support [v12,01/21] clk: Always use the supplied struct clk [v12,02/21] clk: Check that ops of composite clock components exist before calling [v12,03/21] clk: Unconditionally recursively en-/dis-able clocks [v12,04/21] clk: Fix clk_get_by_* handling of index [v12,05/21] clk: Add K210 pll support [v12,06/21] clk: Add a bypass clock for K210 [v12,07/21] clk: Add K210 clock support [v12,08/21] dm: Add support for simple-pm-bus [v12,09/21] dm: Fix error handling for dev_read_addr_ptr [v12,10/21] reset: Add generic reset driver [v12,11/21] lib: Always set errno in hcreate_r [v12,12/21] riscv: Add headers for asm/global_data.h [v12,13/21] riscv: Clear pending interrupts before enabling IPIs [v12,14/21] riscv: Clean up IPI initialization code [v12,15/21] riscv: Add option to support RISC-V privileged spec 1.9 [v12,16/21] riscv: Allow use of reset drivers [v12,17/21] riscv: Try to get cpu frequency from a "clocks" node if it exists [v12,18/21] riscv: Enable cpu clock if it is present [v12,19/21] riscv: Add device tree for K210 and Sipeed Maix BitM [v12,20/21] doc: riscv: Add documentation for Sipeed Maix Bit [v12,21/21] riscv: Add Sipeed Maix support

[v12,15/21] riscv: Add option to support RISC-V privileged spec 1.9

Commit Message

Patch