diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..b2807c33d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_AX25_AE350
 	bool "Support ax25-ae350"
 
+config TARGET_NUCLEI_HBIRD
+	bool "Support Nuclei HBird"
+
 config TARGET_MICROCHIP_ICICLE
 	bool "Support Microchip PolarFire-SoC Icicle Board"
 
@@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/fu540/Kconfig"
+source "board/nuclei/hbird/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 4f30e6936f..da86846f11 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_NUCLEI_HBIRD) += nuclei-hbird.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/nuclei-hbird.dts b/arch/riscv/dts/nuclei-hbird.dts
new file mode 100644
index 0000000000..39d76b63ba
--- /dev/null
+++ b/arch/riscv/dts/nuclei-hbird.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 22020 Nuclei System Technologies */
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		32768
+
+/dts-v1/;
+
+/ {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "nuclei,ux600";
+  model = "nuclei,ux600";
+
+  chosen {
+     bootargs = "earlycon=sbi";
+     stdout-path = "serial0";
+  };
+
+  cpus {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    timebase-frequency = <RTCCLK_FREQ>;
+    cpu0: cpu at 0 {
+      device_type = "cpu";
+      reg = <0>;
+      status = "okay";
+      compatible = "riscv";
+      riscv,isa = "rv64imac";
+      mmu-type = "riscv,sv39";
+      clock-frequency = <8000000>;
+      cpu0_intc: interrupt-controller {
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        compatible = "riscv,cpu-intc";
+      };
+    };
+  };
+
+  memory at A0000000 {
+    device_type = "memory";
+    reg = <0x0 0xA0000000 0x0 0x10000000>;
+  };
+
+  soc {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    compatible = "nuclei,ux600", "simple-bus";
+    ranges;
+  };
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <8000000>;
+		clock-output-names = "hfclk";
+	};
+
+  console {
+		u-boot,dm-pre-reloc;
+		compatible = "sbi,console";
+  };
+
+  plic0: interrupt-controller at 8000000 {
+		#interrupt-cells = <1>;
+		compatible = "riscv,plic0";
+		interrupt-controller;
+        riscv,ndev = <53>;
+		interrupts-extended =
+			<&cpu0_intc 11 &cpu0_intc 9>;
+		reg = <0x0 0x8000000 0x0 0x4000000>;
+	};
+
+	uart0: serial at 10013000 {
+        compatible = "sifive,uart0";
+        reg = <0x0 0x10013000 0x0 0x1000>;
+        interrupt-parent = <&plic0>;
+        interrupts = <4>;
+        status = "disabled";
+	};
+
+	uart1: serial at 10023000 {
+        compatible = "sifive,uart0";
+        reg = <0x0 0x10023000 0x0 0x1000>;
+        interrupt-parent = <&plic0>;
+        interrupts = <5>;
+        status = "okay";
+	};
+
+		qspi0: spi at 10014000 {
+			compatible = "sifive,spi0";
+			reg = <0x0 0x10014000 0x0 0x1000>;
+			#interrupt-parent = <&plic0>;
+			#interrupts = <51>;
+			clocks = <&hfclk>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			flash at 0 {
+				compatible = "gd25q32", "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+		//		m25p,fast-read;
+				#spi-tx-bus-width = <1>;
+				#spi-rx-bus-width = <1>;
+			};
+		};
+
+		qspi2: spi at 10034000 {
+			compatible = "sifive,spi0";
+			reg = <0x0 0x10034000 0x0 0x1000>;
+			#interrupt-parent = <&plic0>;
+			#interrupts = <6>;
+			clocks = <&hfclk>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			mmc at 0 {
+				compatible = "mmc-spi-slot";
+				reg = <0>;
+				spi-max-frequency = <8000000>;
+				voltage-ranges = <3300 3300>;
+				disable-wp;
+			};
+		};
+
+
+};
diff --git a/board/nuclei/hbird/Kconfig b/board/nuclei/hbird/Kconfig
new file mode 100644
index 0000000000..697182ba02
--- /dev/null
+++ b/board/nuclei/hbird/Kconfig
@@ -0,0 +1,53 @@
+if TARGET_NUCLEI_HBIRD
+
+config SYS_BOARD
+	default "hbird"
+
+config SYS_VENDOR
+	default "nuclei"
+
+config SYS_CPU
+	default "generic"
+
+config SYS_CONFIG_NAME
+	default "nuclei-hbird"
+
+config SYS_TEXT_BASE
+	default 0xA0000000 if !RISCV_SMODE
+	default 0xA0200000 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select GENERIC_RISCV
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_SF
+	imply CLK_SIFIVE
+	imply CLK_SIFIVE_FU540_PRCI
+	imply DOS_PARTITION
+	imply IP_DYN
+	imply MACB
+	imply MII
+	imply NET_RANDOM_ETHADDR
+	imply PHY_LIB
+	imply PHY_MSCC
+	imply SIFIVE_SERIAL
+	imply SPI
+	imply SPI_SIFIVE
+	imply SPI_FLASH
+	imply SPI_FLASH_ISSI
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
+	imply DM_GPIO
+	imply SIFIVE_GPIO
+	imply CMD_GPIO
+	imply SMP
+
+endif
diff --git a/board/nuclei/hbird/MAINTAINERS b/board/nuclei/hbird/MAINTAINERS
new file mode 100644
index 0000000000..c88e1286f0
--- /dev/null
+++ b/board/nuclei/hbird/MAINTAINERS
@@ -0,0 +1,6 @@
+Nuclei HBird Platform
+M:	Ruigang Wan <rgwan at nucleisys.com>
+S:	Maintained
+F:	board/nuclei/hbird/
+F:	include/configs/nuclei-hbird.h
+F:	configs/hbird_defconfig
diff --git a/board/nuclei/hbird/Makefile b/board/nuclei/hbird/Makefile
new file mode 100644
index 0000000000..aa76c44da5
--- /dev/null
+++ b/board/nuclei/hbird/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 Nuclei System Technologies
+
+obj-y	+= hbird.o
diff --git a/board/nuclei/hbird/hbird.c b/board/nuclei/hbird/hbird.c
new file mode 100644
index 0000000000..7c8250b474
--- /dev/null
+++ b/board/nuclei/hbird/hbird.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Nuclei System Technologies
+ *
+ * Authors:
+ *   Ruigang Wan <rgwan at nucleisys.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+
+int board_init(void)
+{
+	/* Set Pinmux to enable QSPI2 for SD boot */
+	writel (0x01, (void *)0x10034000);
+	writel (0xec000000, (void *)0x10012008);
+	writel (0x10000000, (void *)0x10012004);
+	writel (0xfc030000, (void *)0x10012038);
+	writel (0x00, (void *)0x10034000); /* NUSPI Prescaler = 4 */
+	__asm__ __volatile__ ("fence w,o" : : : "memory");
+
+	printf ("Board: Initialized\n");
+	return 0;
+}
diff --git a/configs/nuclei_hbird_defconfig b/configs/nuclei_hbird_defconfig
new file mode 100644
index 0000000000..2c4607aaae
--- /dev/null
+++ b/configs/nuclei_hbird_defconfig
@@ -0,0 +1,20 @@
+CONFIG_RISCV=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_NUCLEI_HBIRD=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_MISC_INIT_R=n
+CONFIG_RISCV_SBI_CONSOLE=y
+CONFIG_SBI_V01=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_DEFAULT_DEVICE_TREE="nuclei-hbird"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_FAT_WRITE=y
+
diff --git a/include/configs/nuclei-hbird.h b/include/configs/nuclei-hbird.h
new file mode 100644
index 0000000000..51134adaf9
--- /dev/null
+++ b/include/configs/nuclei-hbird.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Nuclei System Technology
+ *
+ * Authors:
+ *   Ruigang Wan <rgwan at nucleisys.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE		0xA0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0xA0200000
+
+/* Environment options */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"kernel_addr_r=0xA4000000\0" \
+	"fdt_addr_r=0xA8000000\0" \
+	"scriptaddr=0xA8100000\0" \
+	"pxefile_addr_r=0xA8200000\0" \
+	"ramdisk_addr_r=0xA8300000\0" \
+	BOOTENV
+
+#define CONFIG_PREBOOT \
+	"setenv fdt_addr ${fdtcontroladdr};" \
+	"fdt addr ${fdtcontroladdr};"
+
+#endif /* __CONFIG_H */
