diff mbox series

[v10,03/18] riscv: Add _image_binary_end for SPL

Message ID	20200514115258.21042-4-pragnesh.patel@sifive.com
State	Superseded
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: pragnesh.patel at sifive.com (Pragnesh Patel) Date: Thu, 14 May 2020 17:22:41 +0530 Subject: [PATCH v10 03/18] riscv: Add _image_binary_end for SPL In-Reply-To: <20200514115258.21042-1-pragnesh.patel@sifive.com> References: <20200514115258.21042-1-pragnesh.patel@sifive.com> Message-ID: <20200514115258.21042-4-pragnesh.patel@sifive.com>
Series	RISC-V SiFive FU540 support SPL \| expand [v10,00/18] RISC-V SiFive FU540 support SPL [v10,01/18] misc: add driver for the SiFive otp controller [v10,02/18] riscv: sifive: fu540: Use OTP DM driver for serial environment variable [v10,03/18] riscv: Add _image_binary_end for SPL [v10,04/18] lib: Makefile: build crc7.c when CONFIG_MMC_SPI [v10,05/18] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files [v10,06/18] sifive: fu540: add ddr driver [v10,07/18] sifive: dts: fu540: Add DDR controller and phy register settings [v10,08/18] riscv: sifive: dts: fu540: add U-Boot dmc node [v10,09/18] clk: sifive: fu540-prci: Add clock enable and disable ops [v10,10/18] clk: sifive: fu540-prci: Add ddr clock initialization [v10,11/18] clk: sifive: fu540-prci: Release ethernet clock reset [v10,12/18] riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux [v10,13/18] riscv: cpu: fu540: Add support for cpu fu540 [v10,14/18] riscv: sifive: fu540: add SPL configuration [v10,15/18] sifive: fu540: Add sample SD gpt partition layout [v10,16/18] sifive: fu540: Add U-Boot proper sector start [v10,17/18] configs: fu540: Add config options for U-Boot SPL [v10,18/18] doc: sifive: fu540: Add description for OpenSBI generic platform

Commit Message

Pragnesh Patel May 14, 2020, 11:52 a.m. UTC

For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
Reviewed-by: Anup Patel <anup.patel at wdc.com>
Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Bin Meng <bmeng.cn at gmail.com>
---
 arch/riscv/cpu/u-boot-spl.lds | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 955dd3106d..d0495ce248 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -72,6 +72,7 @@  SECTIONS
 	. = ALIGN(4);
 
 	_end = .;
+	_image_binary_end = .;
 
 	.bss : {
 		__bss_start = .;