diff mbox series

[v10,13/18] riscv: cpu: fu540: Add support for cpu fu540

Message ID 20200514115258.21042-14-pragnesh.patel@sifive.com
State Superseded
Headers show
Series RISC-V SiFive FU540 support SPL | expand

Commit Message

Pragnesh Patel May 14, 2020, 11:52 a.m. UTC 
Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
 arch/riscv/Kconfig                       |  1 +
 arch/riscv/cpu/fu540/Kconfig             | 15 ++++++++++
 arch/riscv/cpu/fu540/Makefile            |  7 +++++
 arch/riscv/cpu/fu540/cpu.c               | 22 ++++++++++++++
 arch/riscv/cpu/fu540/dram.c              | 38 ++++++++++++++++++++++++
 arch/riscv/include/asm/arch-fu540/clk.h  | 14 +++++++++
 arch/riscv/include/asm/arch-fu540/gpio.h | 38 ++++++++++++++++++++++++
 board/sifive/fu540/Kconfig               |  2 +-
 8 files changed, 136 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/fu540/Kconfig
 create mode 100644 arch/riscv/cpu/fu540/Makefile
 create mode 100644 arch/riscv/cpu/fu540/cpu.c
 create mode 100644 arch/riscv/cpu/fu540/dram.c
 create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
 create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h

Comments

Bin Meng May 17, 2020, 12:59 p.m. UTC | #1 
On Thu, May 14, 2020 at 7:54 PM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> Add SiFive fu540 cpu to support RISC-V arch
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> ---
>  arch/riscv/Kconfig                       |  1 +
>  arch/riscv/cpu/fu540/Kconfig             | 15 ++++++++++
>  arch/riscv/cpu/fu540/Makefile            |  7 +++++
>  arch/riscv/cpu/fu540/cpu.c               | 22 ++++++++++++++
>  arch/riscv/cpu/fu540/dram.c              | 38 ++++++++++++++++++++++++
>  arch/riscv/include/asm/arch-fu540/clk.h  | 14 +++++++++
>  arch/riscv/include/asm/arch-fu540/gpio.h | 38 ++++++++++++++++++++++++
>  board/sifive/fu540/Kconfig               |  2 +-
>  8 files changed, 136 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/cpu/fu540/Kconfig
>  create mode 100644 arch/riscv/cpu/fu540/Makefile
>  create mode 100644 arch/riscv/cpu/fu540/cpu.c
>  create mode 100644 arch/riscv/cpu/fu540/dram.c
>  create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h
>  create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fb5fe5afff..3044609971 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -57,6 +57,7 @@ source "board/sifive/fu540/Kconfig"
>  # platform-specific options below
>  source "arch/riscv/cpu/ax25/Kconfig"
>  source "arch/riscv/cpu/generic/Kconfig"
> +source "arch/riscv/cpu/fu540/Kconfig"

nits: please insert this line after the ax25 one by following the
alphabetical order

>
>  # architecture-specific options below
>

Other than that,
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
Tested-by: Bin Meng <bmeng.cn at gmail.com>
Pragnesh Patel May 17, 2020, 2:30 p.m. UTC | #2 
Hi Bin,

>-----Original Message-----
>From: Bin Meng <bmeng.cn at gmail.com>
>Sent: 17 May 2020 18:30
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul
>Walmsley <paul.walmsley at sifive.com>; Jagan Teki
><jagan at amarulasolutions.com>; Anup Patel <anup.patel at wdc.com>; Sagar
>Kadam <sagar.kadam at sifive.com>; Rick Chen <rick at andestech.com>; Palmer
>Dabbelt <palmer at dabbelt.com>; Lukas Auer
><lukas.auer at aisec.fraunhofer.de>; Simon Glass <sjg at chromium.org>
>Subject: Re: [PATCH v10 13/18] riscv: cpu: fu540: Add support for cpu fu540
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Thu, May 14, 2020 at 7:54 PM Pragnesh Patel
><pragnesh.patel at sifive.com> wrote:
>>
>> Add SiFive fu540 cpu to support RISC-V arch
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>>  arch/riscv/Kconfig                       |  1 +
>>  arch/riscv/cpu/fu540/Kconfig             | 15 ++++++++++
>>  arch/riscv/cpu/fu540/Makefile            |  7 +++++
>>  arch/riscv/cpu/fu540/cpu.c               | 22 ++++++++++++++
>>  arch/riscv/cpu/fu540/dram.c              | 38 ++++++++++++++++++++++++
>>  arch/riscv/include/asm/arch-fu540/clk.h  | 14 +++++++++
>> arch/riscv/include/asm/arch-fu540/gpio.h | 38 ++++++++++++++++++++++++
>>  board/sifive/fu540/Kconfig               |  2 +-
>>  8 files changed, 136 insertions(+), 1 deletion(-)  create mode 100644
>> arch/riscv/cpu/fu540/Kconfig  create mode 100644
>> arch/riscv/cpu/fu540/Makefile  create mode 100644
>> arch/riscv/cpu/fu540/cpu.c  create mode 100644
>> arch/riscv/cpu/fu540/dram.c  create mode 100644
>> arch/riscv/include/asm/arch-fu540/clk.h
>>  create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index
>> fb5fe5afff..3044609971 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -57,6 +57,7 @@ source "board/sifive/fu540/Kconfig"
>>  # platform-specific options below
>>  source "arch/riscv/cpu/ax25/Kconfig"
>>  source "arch/riscv/cpu/generic/Kconfig"
>> +source "arch/riscv/cpu/fu540/Kconfig"
>
>nits: please insert this line after the ax25 one by following the alphabetical
>order

Will update in v11.

>
>>
>>  # architecture-specific options below
>>
>
>Other than that,
>Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
>Tested-by: Bin Meng <bmeng.cn at gmail.com>

Thanks for the review and testing.
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5afff..3044609971 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -57,6 +57,7 @@  source "board/sifive/fu540/Kconfig"
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
 
 # architecture-specific options below
 
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
new file mode 100644
index 0000000000..e9302e87c0
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -0,0 +1,15 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn at gmail.com>
+
+config SIFIVE_FU540
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER
+	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply CMD_CPU
+	imply SPL_CPU_SUPPORT
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
new file mode 100644
index 0000000000..44700d998c
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -0,0 +1,7 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel at sifive.com>
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/fu540/cpu.c b/arch/riscv/cpu/fu540/cpu.c
new file mode 100644
index 0000000000..13a69ef0cc
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cpu.c
@@ -0,0 +1,22 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn at gmail.com>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
new file mode 100644
index 0000000000..1dc77efeca
--- /dev/null
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -0,0 +1,38 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn at gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top > SZ_4G)
+		return SZ_4G;
+#endif
+	return gd->ram_top;
+}
diff --git a/arch/riscv/include/asm/arch-fu540/clk.h b/arch/riscv/include/asm/arch-fu540/clk.h
new file mode 100644
index 0000000000..d71ed4357c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/clk.h
@@ -0,0 +1,14 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel at sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h
new file mode 100644
index 0000000000..0d16c59ca6
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/gpio.h
@@ -0,0 +1,38 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_platdata {
+	void *base;     /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+		(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index d41c305227..eb5ba3123d 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -7,7 +7,7 @@  config SYS_VENDOR
 	default "sifive"
 
 config SYS_CPU
-	default "generic"
+	default "fu540"
 
 config SYS_CONFIG_NAME
 	default "sifive-fu540"