diff mbox series

[v2,03/12] mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM

Message ID 20200514095912.14428-4-sr@denx.de
State Accepted
Commit 2eed3dca229e97aa03954ee5178457c4f2f8cfdb
Headers show
Series mips: Add initial Octeon MIPS64 base support | expand

Commit Message

Stefan Roese May 14, 2020, 9:59 a.m. UTC 
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <sr at denx.de>

---

Changes in v2:
- Restructure patch by adding empty functions to asm/cm.h instead

 arch/mips/include/asm/cm.h | 12 ++++++++++++
 arch/mips/lib/cache.c      |  2 --
 2 files changed, 12 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 8f37471f81..06d721d228 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -40,6 +40,7 @@ 
 
 #include <asm/io.h>
 
+#if CONFIG_IS_ENABLED(MIPS_CM)
 static inline void *mips_cm_base(void)
 {
 	return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
@@ -55,6 +56,17 @@  static inline unsigned long mips_cm_l2_line_size(void)
 	line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
 	return line_sz ? (2 << line_sz) : 0;
 }
+#else
+static inline void *mips_cm_base(void)
+{
+	return NULL;
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+	return 0;
+}
+#endif
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1a8c87d094..fdffe9493b 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -7,9 +7,7 @@ 
 #include <common.h>
 #include <cpu_func.h>
 #include <asm/cacheops.h>
-#ifdef CONFIG_MIPS_L2_CACHE
 #include <asm/cm.h>
-#endif
 #include <asm/io.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>