diff --git a/MAINTAINERS b/MAINTAINERS
index ec59ce8b88..7f4c325df4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -752,6 +752,12 @@ M:	Ezequiel Garcia <ezequiel at collabora.com>
 S:	Maintained
 F:	arch/mips/mach-jz47xx/
 
+MIPS Octeon
+M:	Aaron Williams <awilliams at marvell.com>
+S:	Maintained
+F:	arch/mips/mach-octeon/
+F:	arch/mips/include/asm/arch-octeon/
+
 MMC
 M:	Peng Fan <peng.fan at nxp.com>
 S:	Maintained
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 48e754cc46..bc5ad0c3ff 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -106,6 +106,25 @@ config ARCH_JZ47XX
 	select OF_CONTROL
 	select DM
 
+config ARCH_OCTEON
+	bool "Support Marvell Octeon CN7xxx platforms"
+	select CPU_CAVIUM_OCTEON
+	select DISPLAY_CPUINFO
+	select DMA_ADDR_T_64BIT
+	select DM
+	select DM_SERIAL
+	select MIPS_INIT_STACK_IN_SRAM
+	select MIPS_L2_CACHE
+	select MIPS_TUNE_OCTEON3
+	select MIPS_SRAM_INIT
+	select ROM_EXCEPTION_VECTORS
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS64_OCTEON
+	select PHYS_64BIT
+	select OF_CONTROL
+	select OF_LIVE
+	imply CMD_DM
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select DM
@@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mtmips/Kconfig"
+source "arch/mips/mach-octeon/Kconfig"
 
 if MIPS
 
@@ -233,6 +253,14 @@ config CPU_MIPS64_R6
 	  Choose this option to build a kernel for release 6 or later of the
 	  MIPS64 architecture.
 
+config CPU_MIPS64_OCTEON
+	bool "Marvell Octeon series of CPUs"
+	depends on SUPPORTS_CPU_MIPS64_OCTEON
+	select 64BIT
+	help
+	 Choose this option for Marvell Octeon CPUs.  These CPUs are between
+	 MIPS64 R5 and R6 with other extensions.
+
 endchoice
 
 menu "General setup"
@@ -398,6 +426,12 @@ config SUPPORTS_CPU_MIPS64_R2
 config SUPPORTS_CPU_MIPS64_R6
 	bool
 
+config SUPPORTS_CPU_MIPS64_OCTEON
+	bool
+
+config CPU_CAVIUM_OCTEON
+	bool
+
 config CPU_MIPS32
 	bool
 	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
@@ -405,6 +439,7 @@ config CPU_MIPS32
 config CPU_MIPS64
 	bool
 	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
+	default y if CPU_MIPS64_OCTEON
 
 config MIPS_TUNE_4KC
 	bool
@@ -421,6 +456,9 @@ config MIPS_TUNE_34KC
 config MIPS_TUNE_74KC
 	bool
 
+config MIPS_TUNE_OCTEON3
+	bool
+
 config 32BIT
 	bool
 
@@ -453,6 +491,11 @@ config MIPS_SRAM_INIT
 	  before it can be used. If enabled, a function mips_sram_init() will
 	  be called just before setup_stack_gd.
 
+config DMA_ADDR_T_64BIT
+	bool
+	help
+	 Select this to enable 64-bit DMA addressing
+
 config SYS_DCACHE_SIZE
 	int
 	default 0
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index af3f227436..6502aebd29 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MTMIPS) += mtmips
 machine-$(CONFIG_ARCH_MSCC) += mscc
+machine-${CONFIG_ARCH_OCTEON} += octeon
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
@@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
 arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
+arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
 
 # Allow extra optimization for specific CPUs/SoCs
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
@@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
 tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
 tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
 tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
+tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
 
 # Include default header files
 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
new file mode 100644
index 0000000000..9fd4c6cb0a
--- /dev/null
+++ b/arch/mips/mach-octeon/Kconfig
@@ -0,0 +1,53 @@
+menu "Octeon platforms"
+	depends on ARCH_OCTEON
+
+config SYS_SOC
+	string
+	default "octeon"
+
+config OCTEON_CN7XXX
+	bool "Octeon CN7XXX SoC"
+
+config OCTEON_CN70XX
+	bool "Octeon CN70XX SoC"
+	select OCTEON_CN7XXX
+
+config OCTEON_CN73XX
+	bool "Octeon CN73XX SoC"
+	select OCTEON_CN7XXX
+
+config OCTEON_CN78XX
+	bool "Octeon CN78XX SoC"
+	select OCTEON_CN7XXX
+
+choice
+	prompt "Octeon MIPS family select"
+
+config SOC_OCTEON3
+	bool "Octeon III family"
+	help
+	 This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
+	 and CNF75XX.
+
+endchoice
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 128
+
+config SYS_ICACHE_SIZE
+	default	79872
+
+config SYS_ICACHE_LINE_SIZE
+	default 128
+
+config MIPS_INIT_JUMP_OFFSET
+	hex
+	default 0xffffffffbfc00000
+	help
+	 This specifies the address where U-Boot starts exceution.
+	 In this case its the flash base address of the bootbus.
+
+endmenu
diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
new file mode 100644
index 0000000000..2e37ca572c
--- /dev/null
+++ b/arch/mips/mach-octeon/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2019 Marvell, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += lowlevel_init.o
+obj-y += cache.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
new file mode 100644
index 0000000000..481da3a27a
--- /dev/null
+++ b/arch/mips/mach-octeon/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <common.h>
+
+/*
+ * The Octeon platform is cache coherent and cache flushes and invalidates
+ * are not needed. Define some platform specific empty flush_foo()
+ * functions here to overwrite the _weak common function as a no-op.
+ * This effectively disables all cache operations.
+ */
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+}
diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c
new file mode 100644
index 0000000000..2d90c4cbe1
--- /dev/null
+++ b/arch/mips/mach-octeon/clock.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ */
+
+#include <common.h>
+#include <mach/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong notrace get_tbclk(void)
+{
+	return gd->cpu_clk;
+}
+
+int octeon_get_timer_freq(void)
+{
+	return gd->cpu_clk;
+}
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeon_get_io_clock(void)
+{
+	return gd->bus_clk;
+}
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
new file mode 100644
index 0000000000..15c6769695
--- /dev/null
+++ b/arch/mips/mach-octeon/cpu.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/cavm-reg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_clocks(void)
+{
+	const u64 ref_clock = PLL_REF_CLK;
+	union cavm_rst_boot rst_boot;
+
+	rst_boot.u = ioread64(CAVM_RST_BOOT);
+	gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
+	gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
+
+	debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+
+	return 0;
+}
+
+/* Early mach init code run from flash */
+int mach_cpu_init(void)
+{
+	/* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
+	/* ToDo: Move this to an early running bus (bootbus) DM driver */
+	clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
+
+	/* Get clocks and store them in GD */
+	get_clocks();
+
+	return 0;
+}
+
+/**
+ * Returns number of cores
+ *
+ * @return	number of CPU cores for the specified node
+ */
+static int cavm_octeon_num_cores(void)
+{
+	return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
+}
+
+int print_cpuinfo(void)
+{
+	printf("SoC:   Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
+
+	return 0;
+}
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
new file mode 100644
index 0000000000..2cb8a81a30
--- /dev/null
+++ b/arch/mips/mach-octeon/dram.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/*
+	 * No DDR init yet -> run in L2 cache
+	 */
+	gd->ram_size = (4 << 20);
+	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->bd->bi_dram[1].size = 0;
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return gd->ram_top;
+}
diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h
new file mode 100644
index 0000000000..59b75008a2
--- /dev/null
+++ b/arch/mips/mach-octeon/include/ioremap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_OCTEON_IOREMAP_H
+#define __ASM_MACH_OCTEON_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+					     phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	return (void __iomem *)(XKPHYS | offset);
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return 0;
+}
+
+#define _page_cachable_default	_CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h
new file mode 100644
index 0000000000..b961e54956
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier:    GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CAVM_REG_H__
+
+/* Register offsets */
+#define CAVM_CIU_FUSE			((u64 *)0x80010100000001a0)
+#define CAVM_MIO_BOOT_REG_CFG0		((u64 *)0x8001180000000000)
+#define CAVM_RST_BOOT			((u64 *)0x8001180006001600)
+
+/* Register structs */
+
+/**
+ * Register (RSL) rst_boot
+ *
+ * RST Boot Register
+ */
+union cavm_rst_boot {
+	u64 u;
+	struct cavm_rst_boot_s {
+		u64 chipkill                         : 1;
+		u64 jtcsrdis                         : 1;
+		u64 ejtagdis                         : 1;
+		u64 romen                            : 1;
+		u64 ckill_ppdis                      : 1;
+		u64 jt_tstmode                       : 1;
+		u64 vrm_err                          : 1;
+		u64 reserved_37_56                   : 20;
+		u64 c_mul                            : 7;
+		u64 pnr_mul                          : 6;
+		u64 reserved_21_23                   : 3;
+		u64 lboot_oci                        : 3;
+		u64 lboot_ext                        : 6;
+		u64 lboot                            : 10;
+		u64 rboot                            : 1;
+		u64 rboot_pin                        : 1;
+	} s;
+};
+
+#endif /* __CAVM_REG_H__ */
diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h
new file mode 100644
index 0000000000..a844a222c9
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/clock.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier:    GPL-2.0 */
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __CLOCK_H__
+
+/** System PLL reference clock */
+#define PLL_REF_CLK                     50000000        /* 50 MHz */
+#define NS_PER_REF_CLK_TICK             (1000000000 / PLL_REF_CLK)
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeon_get_io_clock(void);
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeon_get_core_clock(void);
+
+#endif /* __CLOCK_H__ */
diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S
new file mode 100644
index 0000000000..ea90e6b8d6
--- /dev/null
+++ b/arch/mips/mach-octeon/lowlevel_init.S
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+
+	.set noreorder
+
+LEAF(mips_sram_init)
+
+        move    s0, ra
+
+	bal	__dummy
+	 nop
+
+__dummy:
+	/* Get the actual address that we are running at */
+	PTR_LA	a6, _start		/* Linked address of _start */
+	PTR_LA	a7, __dummy
+	dsubu	t1, a7, a6		/* offset of __dummy label from _start*/
+	dsubu	t0, ra, t1		/* t0 now has actual address of _start*/
+
+	PTR_LI	t1, CONFIG_SYS_TEXT_BASE
+
+	/* Calculate end address of copy loop */
+	PTR_LI	s5, CONFIG_BOARD_SIZE_LIMIT
+	daddu	t2, s5, t0	/* t2 = end address */
+	daddiu	t2, t2, 127
+	ins	t2, zero, 0, 7	/* Round up to cache line for memcpy */
+
+	/* Copy ourself to the L2 cache from flash, 32 bytes at a time */
+1:
+	ld	a0, 0(t0)
+	ld	a1, 8(t0)
+	ld	a2, 16(t0)
+	ld	a3, 24(t0)
+	sd	a0, 0(t1)
+	sd	a1, 8(t1)
+	sd	a2, 16(t1)
+	sd	a3, 24(t1)
+	addiu	t0, 32
+	bne	t0, t2, 1b
+	addiu	t1, 32
+
+	sync
+	synci	0(zero)
+
+	PTR_LA	t9, uboot_in_cache
+	j	t9
+	 nop
+
+uboot_in_cache:
+
+	/*
+	 * Return to start.S now running from TEXT_BASE, which points
+	 * to DRAM address space, which effectively is L2 cache now.
+	 * This speeds up the init process extremely, especially the
+	 * DDR init code.
+	 */
+	jr	s0
+	 nop
+
+	END(mips_sram_init)
+
+LEAF(lowlevel_init)
+	jr	ra
+	 nop
+	END(lowlevel_init)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 253c46159b..e254c11d66 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
 CONFIG_CPM2
 CONFIG_CPU_ARMV8
-CONFIG_CPU_CAVIUM_OCTEON
 CONFIG_CPU_FREQ_HZ
 CONFIG_CPU_HAS_LLSC
 CONFIG_CPU_HAS_PREFETCH
