From patchwork Wed May 13 19:15:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Urja Rannikko X-Patchwork-Id: 245747 List-Id: U-Boot discussion From: urjaman at gmail.com (Urja Rannikko) Date: Wed, 13 May 2020 19:15:20 +0000 Subject: [PATCH 1/4] rockchip: spl: veyron speedy boots from SPI In-Reply-To: <20200513191523.3141-1-urjaman@gmail.com> References: <20200513191523.3141-1-urjaman@gmail.com> Message-ID: <20200513191523.3141-2-urjaman@gmail.com> Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 0b76af6080..2c2b4ea5c0 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -49,7 +49,8 @@ u32 spl_boot_device(void) #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))