From patchwork Tue May 12 09:58:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 245659 List-Id: U-Boot discussion From: david.wu at rock-chips.com (David Wu) Date: Tue, 12 May 2020 17:58:52 +0800 Subject: [RESEND PATCH v2 10/11] net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip In-Reply-To: <20200512095603.29126-1-david.wu@rock-chips.com> References: <20200512095603.29126-1-david.wu@rock-chips.com> Message-ID: <20200512095852.29520-1-david.wu@rock-chips.com> The Rockchip CSR clock range is from 100M to 150M, add EQOS_MAC_MDIO_ADDRESS_CR_100_150. Signed-off-by: David Wu Reviewed-by: Patrice Chotard --- Changes in v2: - None drivers/net/dwc_eth_qos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index def2706271..39f8452c17 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -12,10 +12,10 @@ #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 +#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 - struct eqos_config { bool reg_access_always_ok; int mdio_wait;