From patchwork Tue May 12 09:39:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 245642 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Tue, 12 May 2020 17:39:01 +0800 Subject: [PATCH V2 5/5] imx: imx8mp_evk: fix boot issue In-Reply-To: <20200512093901.14831-1-peng.fan@nxp.com> References: <20200512093901.14831-1-peng.fan@nxp.com> Message-ID: <20200512093901.14831-6-peng.fan@nxp.com> The u-boot-spl.bin pad with ddr firmware conflicts with the CONFIG_MALLOC_F_ADDR area, the ddr firmware will be overwritten by malloc in SPL stage and cause ddr initialization not able to finish. So update the related addresses to fix the issue. Reported-by: Fabio Estevam Signed-off-by: Peng Fan --- configs/imx8mp_evk_defconfig | 3 ++- include/configs/imx8mp_evk.h | 12 +++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 44b2935f69..3189b2ad99 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -4,7 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 CONFIG_SYS_I2C_MXC_I2C1=y diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 80e5738961..1b81ffc5f4 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -23,16 +23,14 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x990000 -#define CONFIG_SPL_BSS_START_ADDR 0x0095e000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +#define CONFIG_SPL_STACK 0x960000 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_MALLOC_F_ADDR 0x940000 - #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC