diff mbox series

[5/8] CLK: ARC: HSDK: prepare for multiple clock maps support

Message ID 20200508124420.31788-6-Eugeniy.Paltsev@synopsys.com
State Accepted
Commit debfe3844502d3a2d7a10c6bb21b5f43a3f1d249
Headers show
Series CLK: ARC: HSDK: add separate clock map for HSDK-4xD | expand

Commit Message

Eugeniy Paltsev May 8, 2020, 12:44 p.m. UTC 
The clock trees of HSDK and HSDK-4xD vary so we need to prepare
CGU driver for multiple clock maps support.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
---
 drivers/clk/clk-hsdk-cgu.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index d7cb4f46242..6aba4587a44 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -227,6 +227,7 @@  struct hsdk_cgu_domain {
 };
 
 struct hsdk_cgu_clk {
+	const struct cgu_clk_map *map;
 	/* CGU block register */
 	void __iomem *cgu_regs;
 	/* CREG block register */
@@ -632,37 +633,47 @@  static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
 	if (sclk->id >= CGU_MAX_CLOCKS)
 		return -EINVAL;
 
-	clk->curr_domain.pll = clock_map[sclk->id].pll_devdata;
-	clk->curr_domain.pll_regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
+	/* clocks missing in current map have their entry zeroed */
+	if (!clk->map[sclk->id].pll_devdata)
+		return -EINVAL;
+
+	clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
+	clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
 	clk->curr_domain.spec_regs = clk->creg_regs;
-	clk->curr_domain.idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
+	clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
 
 	return 0;
 }
 
 static ulong hsdk_cgu_get_rate(struct clk *sclk)
 {
+	struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
 	if (hsdk_prepare_clock_tree_branch(sclk))
 		return -EINVAL;
 
-	return clock_map[sclk->id].get_rate(sclk);
+	return clk->map[sclk->id].get_rate(sclk);
 }
 
 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
 {
+	struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
 	if (hsdk_prepare_clock_tree_branch(sclk))
 		return -EINVAL;
 
-	return clock_map[sclk->id].set_rate(sclk, rate);
+	return clk->map[sclk->id].set_rate(sclk, rate);
 }
 
 static int hsdk_cgu_disable(struct clk *sclk)
 {
+	struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
 	if (hsdk_prepare_clock_tree_branch(sclk))
 		return -EINVAL;
 
-	if (clock_map[sclk->id].disable)
-		return clock_map[sclk->id].disable(sclk);
+	if (clk->map[sclk->id].disable)
+		return clk->map[sclk->id].disable(sclk);
 
 	return -ENOTSUPP;
 }
@@ -679,6 +690,8 @@  static int hsdk_cgu_clk_probe(struct udevice *dev)
 
 	BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
 
+	hsdk_clk->map = clock_map;
+
 	hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
 	if (!hsdk_clk->cgu_regs)
 		return -EINVAL;