From patchwork Mon May 4 14:08:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 245032 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Mon, 4 May 2020 22:08:58 +0800 Subject: [PATCH 09/14] mtd: mxs_nand: fix the gf_13/14 definition issue In-Reply-To: <20200504140903.23602-1-peng.fan@nxp.com> References: <20200504140903.23602-1-peng.fan@nxp.com> Message-ID: <20200504140903.23602-10-peng.fan@nxp.com> From: Han Xu gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/regs-bch.h | 8 ++++---- drivers/mtd/nand/raw/mxs_nand.c | 2 ++ include/mxs_nand.h | 1 + 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h index 4b99edbb3d..664fb9fd4d 100644 --- a/arch/arm/include/asm/mach-imx/regs-bch.h +++ b/arch/arm/include/asm/mach-imx/regs-bch.h @@ -151,9 +151,9 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10) #define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10 -#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) @@ -182,9 +182,9 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) -#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10) #define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10 -#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 #define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index facedf92c5..1b66636a4f 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1474,6 +1474,8 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l) BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET); l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >> BCH_FLASHLAYOUT1_ECCN_OFFSET; + l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >> + BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; } /* diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 1ac628d064..21d68a909d 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -88,6 +88,7 @@ struct mxs_nand_layout { u32 ecc0; u32 datan_size; u32 eccn; + u32 gf_len; }; int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);