From patchwork Sat May 2 08:59:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 244769 List-Id: U-Boot discussion From: sr at denx.de (Stefan Roese) Date: Sat, 2 May 2020 10:59:38 +0200 Subject: [PATCH v1 04/10] mips: traps: Set WG bit in EBase register on Octeon In-Reply-To: <20200502085944.13444-1-sr@denx.de> References: <20200502085944.13444-1-sr@denx.de> Message-ID: <20200502085944.13444-5-sr@denx.de> WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese --- arch/mips/lib/traps.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 8fff7541e3..ccbce97161 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr) saved_ebase = read_c0_ebase() & 0xfffff000; + /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= BIT(11); + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier();