| Message ID | 20200430212140.v3.5.I2f97cd67497c0adb28145096b8dd3534ab29a730@changeid |
|---|---|
| State | Accepted |
| Commit | b4d4f592b243d08791ce582073710444ede48446 |
| Headers | show |
| Series | x86: efi: Add a 64-bit coreboot payload | expand |
On Fri, May 1, 2020 at 11:22 AM Simon Glass <sjg at chromium.org> wrote: > > Make a few adjustments to allow us to build an SPL image for coreboot. > > Signed-off-by: Simon Glass <sjg at chromium.org> > --- > > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/Makefile | 4 +++- > arch/x86/cpu/coreboot/Makefile | 8 +++++++- > arch/x86/cpu/coreboot/coreboot.c | 3 ++- > arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++ > arch/x86/cpu/intel_common/Makefile | 2 ++ > arch/x86/cpu/x86_64/cpu.c | 2 ++ > 6 files changed, 28 insertions(+), 3 deletions(-) > create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> Tested-by: Bin Meng <bmeng.cn at gmail.com>
On Fri, May 1, 2020 at 6:25 PM Bin Meng <bmeng.cn at gmail.com> wrote: > > On Fri, May 1, 2020 at 11:22 AM Simon Glass <sjg at chromium.org> wrote: > > > > Make a few adjustments to allow us to build an SPL image for coreboot. > > > > Signed-off-by: Simon Glass <sjg at chromium.org> > > --- > > > > Changes in v3: None > > Changes in v2: None > > > > arch/x86/cpu/Makefile | 4 +++- > > arch/x86/cpu/coreboot/Makefile | 8 +++++++- > > arch/x86/cpu/coreboot/coreboot.c | 3 ++- > > arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++ > > arch/x86/cpu/intel_common/Makefile | 2 ++ > > arch/x86/cpu/x86_64/cpu.c | 2 ++ > > 6 files changed, 28 insertions(+), 3 deletions(-) > > create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c > > > > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> > Tested-by: Bin Meng <bmeng.cn at gmail.com> applied to u-boot-x86, thanks!
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 307267a8fb..ee0499f5d7 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o +ifndef CONFIG_SYS_COREBOOT +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +endif ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index 35b15bb1da..605f90304e 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -11,8 +11,14 @@ # (C) Copyright 2002 # Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se. +ifndef CONFIG_SPL obj-y += car.o +endif +ifdef CONFIG_SPL_BUILD +obj-y += coreboot_spl.o +else +obj-y += sdram.o +endif obj-y += coreboot.o obj-y += tables.o -obj-y += sdram.o obj-y += timestamp.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 0c4c6348d1..624caf67a6 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -27,7 +27,8 @@ int arch_cpu_init(void) timestamp_init(); - return x86_cpu_init_f(); + return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + x86_cpu_init_f(); } int checkcpu(void) diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c new file mode 100644 index 0000000000..36661871e9 --- /dev/null +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + */ + +#include <common.h> +#include <init.h> + +int dram_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 1736bd2b53..374803b876 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SYS_COREBOOT obj-y += cpu_from_spl.o endif endif +endif diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 90925e46ea..4b64339f25 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -53,6 +53,7 @@ int misc_init_r(void) return 0; } +#ifndef CONFIG_SYS_COREBOOT int checkcpu(void) { return 0; @@ -62,6 +63,7 @@ int print_cpuinfo(void) { return 0; } +#endif int x86_cpu_reinit_f(void) {
Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg at chromium.org> --- Changes in v3: None Changes in v2: None arch/x86/cpu/Makefile | 4 +++- arch/x86/cpu/coreboot/Makefile | 8 +++++++- arch/x86/cpu/coreboot/coreboot.c | 3 ++- arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++ arch/x86/cpu/intel_common/Makefile | 2 ++ arch/x86/cpu/x86_64/cpu.c | 2 ++ 6 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c