| Message ID | 20200430212140.v3.4.Icb053e447a5e46d3f383d85a45118b48614879d4@changeid |
|---|---|
| State | Accepted |
| Commit | fc486371c3696cf246163fc35e79c740a5d7d1b9 |
| Headers | show |
| Series | x86: efi: Add a 64-bit coreboot payload | expand |
On Fri, May 1, 2020 at 11:22 AM Simon Glass <sjg at chromium.org> wrote: > > At present SPL only works on bare-metal builds. With a few tweaks it can > be used for coreboot also. > > Signed-off-by: Simon Glass <sjg at chromium.org> > --- > > Changes in v3: None > Changes in v2: None > > arch/x86/lib/spl.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> Tested-by: Bin Meng <bmeng.cn at gmail.com>
On Fri, May 1, 2020 at 6:25 PM Bin Meng <bmeng.cn at gmail.com> wrote: > > On Fri, May 1, 2020 at 11:22 AM Simon Glass <sjg at chromium.org> wrote: > > > > At present SPL only works on bare-metal builds. With a few tweaks it can > > be used for coreboot also. > > > > Signed-off-by: Simon Glass <sjg at chromium.org> > > --- > > > > Changes in v3: None > > Changes in v2: None > > > > arch/x86/lib/spl.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> > Tested-by: Bin Meng <bmeng.cn at gmail.com> applied to u-boot-x86, thanks!
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 95a89c072d..212b4d596d 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -63,7 +63,7 @@ static int x86_spl_init(void) * is not needed. We could make this a CONFIG option or perhaps * place it immediately below CONFIG_SYS_TEXT_BASE. */ - char *ptr = (char *)0x110000; + __maybe_unused char *ptr = (char *)0x110000; #else struct udevice *punit; #endif @@ -111,7 +111,8 @@ static int x86_spl_init(void) __func__, ret); } -#ifndef CONFIG_TPL +#ifndef CONFIG_SYS_COREBOOT +# ifndef CONFIG_TPL memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); /* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */ @@ -140,7 +141,7 @@ static int x86_spl_init(void) return ret; } mtrr_commit(true); -#else +# else ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit); if (ret) debug("Could not find PUNIT (err=%d)\n", ret); @@ -148,6 +149,7 @@ static int x86_spl_init(void) ret = set_max_freq(); if (ret) debug("Failed to set CPU frequency (err=%d)\n", ret); +# endif #endif return 0; @@ -162,7 +164,7 @@ void board_init_f(ulong flags) debug("Error %d\n", ret); panic("x86_spl_init fail"); } -#ifdef CONFIG_TPL +#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT) gd->bd = malloc(sizeof(*gd->bd)); if (!gd->bd) { printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
At present SPL only works on bare-metal builds. With a few tweaks it can be used for coreboot also. Signed-off-by: Simon Glass <sjg at chromium.org> --- Changes in v3: None Changes in v2: None arch/x86/lib/spl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)