From patchwork Fri Apr 24 20:39:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 238448 List-Id: U-Boot discussion From: Eugeniy.Paltsev at synopsys.com (Eugeniy Paltsev) Date: Fri, 24 Apr 2020 23:39:32 +0300 Subject: [PATCH 11/14] ARC: HSDK-4xD: add CSM configuration support In-Reply-To: <20200424203935.21333-1-Eugeniy.Paltsev@synopsys.com> References: <20200424203935.21333-1-Eugeniy.Paltsev@synopsys.com> Message-ID: <20200424203935.21333-12-Eugeniy.Paltsev@synopsys.com> Add support for CSM enable/disable and CSM relocation via hsdk_init command. We allow to relocate CSM to the beginning of any aperture even if HW support finer granularity. Signed-off-by: Eugeniy Paltsev --- arch/arc/include/asm/arcregs.h | 3 +++ board/synopsys/hsdk/hsdk.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index f3cd4a889ac..516c14e105b 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -51,6 +51,9 @@ #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ +/* CSM auxiliary registers */ +#define ARC_AUX_CSM_ENABLE 0x9A0 + /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index b25b1331874..2cbb59d8092 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -80,6 +80,7 @@ struct hsdk_env_common_ctl { u32_env nvlim; u32_env icache; u32_env dcache; + u32_env csm_location; u32_env l2_cache; }; @@ -132,6 +133,7 @@ static const struct env_map_common env_map_common[] = { { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache }, #if defined(CONFIG_BOARD_HSDK_4XD) { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache }, + { "csm_location", ENV_HEX, true, 0, NO_CCM, &env_common.csm_location }, #endif /* CONFIG_BOARD_HSDK_4XD */ {} }; @@ -299,6 +301,30 @@ static void init_cluster_slc(void) slc_disable(); } +#define CREG_CSM_BASE (CREG_BASE + 0x210) + +static void init_cluster_csm(void) +{ + /* ARC HS38 in HSDK SoC doesn't include CSM */ + if (!is_board_match_config(T_BOARD_HSDK_4XD)) + return; + + if (env_common.csm_location.val == NO_CCM) { + write_aux_reg(ARC_AUX_CSM_ENABLE, 0); + } else { + /* + * CSM base address is 256kByte aligned but we allow to map + * CSM only to aperture start (256MByte aligned) + * The field in CREG_CSM_BASE is in 17:2 bits itself so we need + * to shift it. + */ + u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2; + + write_aux_reg(ARC_AUX_CSM_ENABLE, 1); + writel(csm_base, (void __iomem *)CREG_CSM_BASE); + } +} + static void init_master_icache(void) { if (icache_status()) { @@ -678,6 +704,7 @@ static void do_init_cluster(void) * cores. */ init_cluster_nvlim(); + init_cluster_csm(); init_cluster_slc(); }