| Message ID | 20200424165012.31915-3-s.nawrocki@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | USB host support for Raspberry Pi 4 board | expand |
On Sat, Apr 25, 2020 at 12:51 AM Sylwester Nawrocki <s.nawrocki at samsung.com> wrote: > > There might be hardware configurations where 64-bit data accesses > to XHCI registers are not supported properly. This patch removes > the readq/writeq so always two 32-bit accesses are used to read/write > 64-bit XHCI registers, similarly as it is done in Linux kernel. > > This patch fixes operation of the XHCI controller on RPI4 Broadcom > BCM2711 SoC based board, where the VL805 USB XHCI controller is > connected to the PCIe Root Complex, which is attached to the system > through the SCB bridge. > > Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely > the 64-bit wide register accesses initiated by the CPU are not properly > translated to a sequence of 32-bit PCIe accesses. > xhci_readq(), for example, always returns same value in upper and lower > 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. > > Cc: Sergey Temerkhanov <s.temerkhanov at gmail.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> > --- > Changes since RFC: > - dropped Kconfig option, switched to not using readq/writeq > unconditionally. > --- > include/usb/xhci.h | 8 -------- > 1 file changed, 8 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
On Fri, 2020-04-24 at 18:50 +0200, Sylwester Nawrocki wrote: > There might be hardware configurations where 64-bit data accesses > to XHCI registers are not supported properly. This patch removes > the readq/writeq so always two 32-bit accesses are used to read/write > 64-bit XHCI registers, similarly as it is done in Linux kernel. > > This patch fixes operation of the XHCI controller on RPI4 Broadcom > BCM2711 SoC based board, where the VL805 USB XHCI controller is > connected to the PCIe Root Complex, which is attached to the system > through the SCB bridge. > > Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely > the 64-bit wide register accesses initiated by the CPU are not properly > translated to a sequence of 32-bit PCIe accesses. > xhci_readq(), for example, always returns same value in upper and lower > 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. > > Cc: Sergey Temerkhanov <s.temerkhanov at gmail.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> > --- > Changes since RFC: > - dropped Kconfig option, switched to not using readq/writeq > unconditionally. Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne at suse.de> Regards, Nicolas -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: This is a digitally signed message part URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200427/28bcedf3/attachment.sig>
diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 6017504..c16106a 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) */ static inline u64 xhci_readq(__le64 volatile *regs) { -#if BITS_PER_LONG == 64 - return readq(regs); -#else __u32 *ptr = (__u32 *)regs; u64 val_lo = readl(ptr); u64 val_hi = readl(ptr + 1); return val_lo + (val_hi << 32); -#endif } static inline void xhci_writeq(__le64 volatile *regs, const u64 val) { -#if BITS_PER_LONG == 64 - writeq(val, regs); -#else __u32 *ptr = (__u32 *)regs; u32 val_lo = lower_32_bits(val); /* FIXME */ u32 val_hi = upper_32_bits(val); writel(val_lo, ptr); writel(val_hi, ptr + 1); -#endif } int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
There might be hardware configurations where 64-bit data accesses to XHCI registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit XHCI registers, similarly as it is done in Linux kernel. This patch fixes operation of the XHCI controller on RPI4 Broadcom BCM2711 SoC based board, where the VL805 USB XHCI controller is connected to the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. xhci_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. Cc: Sergey Temerkhanov <s.temerkhanov at gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> --- Changes since RFC: - dropped Kconfig option, switched to not using readq/writeq unconditionally. --- include/usb/xhci.h | 8 -------- 1 file changed, 8 deletions(-)