From patchwork Fri Apr 24 13:47:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 238411 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Fri, 24 Apr 2020 15:47:57 +0200 Subject: [PATCH] clk: stm32mp1: fix CK_MPU calculation Message-ID: <20200424154751.1.Ic2e6fdeb2c6943f077579212f2625f0532a16ceb@changeid> From: Lionel Debieve When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter PLL_MPUDIV. Signed-off-by: Lionel Debieve Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 50df8425bf..0d0ea43fd2 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) case RCC_MPCKSELR_PLL: case RCC_MPCKSELR_PLL_MPUDIV: clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); - if (p == RCC_MPCKSELR_PLL_MPUDIV) { + if ((reg & RCC_SELR_SRC_MASK) == + RCC_MPCKSELR_PLL_MPUDIV) { reg = readl(priv->base + RCC_MPCKDIVR); - clock /= stm32mp1_mpu_div[reg & - RCC_MPUDIV_MASK]; + clock >>= stm32mp1_mpu_div[reg & + RCC_MPUDIV_MASK]; } break; }