From patchwork Wed Apr 22 13:52:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 238324 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Wed, 22 Apr 2020 21:52:30 +0800 Subject: [PATCH 19/24] imx8mm: clock: fix fracpll decode issue In-Reply-To: <20200422135235.14756-1-peng.fan@nxp.com> References: <20200422135235.14756-1-peng.fan@nxp.com> Message-ID: <20200422135235.14756-19-peng.fan@nxp.com> From: Ye Li The fracpll decoding is using the bit definitions for int pll. Most of them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK for fracpll and correct all bit definitions in fracpll decoding. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 2 +- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h index 84ed61d21e..140e8bbabd 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -19,7 +19,7 @@ #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) -#define CLKE_MASK BIT(11) +#define CLKE_MASK BIT(13) #define RST_MASK BIT(9) #define BYPASS_MASK BIT(4) #define MDIV_SHIFT 12 diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index c423ac0058..8c9a6b8b12 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll) } /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ - if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) return 0; - if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + if ((pll_gnrl_ctl & RST_MASK) == 0) return 0; /* * When BYPASS is equal to 1, PLL enters the bypass mode * regardless of the values of RESETB */ - if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + if (pll_gnrl_ctl & BYPASS_MASK) return 24000000u; - if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + if (!(pll_gnrl_ctl & LOCK_STATUS)) { puts("pll not locked\n"); return 0; } - if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK)) + if (!(pll_gnrl_ctl & CLKE_MASK)) return 0; - main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >> - INTPLL_MAIN_DIV_SHIFT; - pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >> - INTPLL_PRE_DIV_SHIFT; - post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >> - INTPLL_POST_DIV_SHIFT; + main_div = (pll_fdiv_ctl0 & MDIV_MASK) >> + MDIV_SHIFT; + pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >> + PDIV_SHIFT; + post_div = (pll_fdiv_ctl0 & SDIV_MASK) >> + SDIV_SHIFT; - k = pll_fdiv_ctl1 & GENMASK(15, 0); + k = pll_fdiv_ctl1 & KDIV_MASK; return lldiv((main_div * 65536 + k) * 24000000ULL, 65536 * pre_div * (1 << post_div));