From patchwork Wed Apr 15 09:00:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 237789 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Wed, 15 Apr 2020 17:00:28 +0800 Subject: [PATCH 5/7] ddr: altera: arria10: Add RAM size check In-Reply-To: <20200415090030.128489-1-ley.foon.tan@intel.com> References: <20200415090030.128489-1-ley.foon.tan@intel.com> Message-ID: <20200415090030.128489-6-ley.foon.tan@intel.com> Add call to get_ram_size() function to check memory range for valid RAM. Signed-off-by: Ley Foon Tan --- drivers/ddr/altera/sdram_arria10.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 6b74423ea789..e3f11984a978 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -17,7 +18,7 @@ #include #include #include -#include +#include #include "sdram_arria10.h" @@ -671,6 +672,27 @@ static int ddr_calibration_sequence(struct altera_sdram_platdata *plat) return 0; } +static void sdram_size_check(struct ram_info *ram) +{ + phys_size_t ram_check = 0; + phys_size_t size = ram->size; + phys_addr_t base = ram->base; + + debug("DDR: Running SDRAM size sanity check\n"); + + while (ram_check < size) { + ram_check += get_ram_size((void *)(base + ram_check), + (phys_size_t)SZ_1G); + } + + if (ram_check != size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + static int altera_sdram_ofdata_to_platdata(struct udevice *dev) { struct altera_sdram_platdata *plat = dev->platdata; @@ -715,6 +737,7 @@ static int altera_sdram_probe(struct udevice *dev) priv->info.base = gd->bd->bi_dram[0].start; priv->info.size = gd->ram_size; + sdram_size_check(&priv->info); return 0; failed: