From patchwork Sun Apr 12 22:03:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 237688 List-Id: U-Boot discussion From: marek.vasut at gmail.com (Marek Vasut) Date: Mon, 13 Apr 2020 00:03:47 +0200 Subject: [PATCH 01/13] net: rtl8139: Register macro cleanup Message-ID: <20200412220359.28224-1-marek.vasut+renesas@gmail.com> Clean up the horrible register definitions in the RTL8139 driver. This does create a couple of checkpatch errors, but the driver is full of them anyway, and those will be cleaned up later. No functional change. Signed-off-by: Marek Vasut Cc: Joe Hershberger Acked-by: Joe Hershberger --- drivers/net/rtl8139.c | 263 ++++++++++++++++++++++++------------------ 1 file changed, 152 insertions(+), 111 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index bb59629f81..9898f20c39 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -99,77 +99,96 @@ #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) /* Symbolic offsets to registers. */ -enum RTL8139_registers { - MAC0=0, /* Ethernet hardware address. */ - MAR0=8, /* Multicast filter. */ - TxStatus0=0x10, /* Transmit status (four 32bit registers). */ - TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ - RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, - ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, - IntrMask=0x3C, IntrStatus=0x3E, - TxConfig=0x40, RxConfig=0x44, - Timer=0x48, /* general-purpose counter. */ - RxMissed=0x4C, /* 24 bits valid, write clears. */ - Cfg9346=0x50, Config0=0x51, Config1=0x52, - TimerIntrReg=0x54, /* intr if gp counter reaches this value */ - MediaStatus=0x58, - Config3=0x59, - MultiIntr=0x5C, - RevisionID=0x5E, /* revision of the RTL8139 chip */ - TxSummary=0x60, - MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, - NWayExpansion=0x6A, - DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, - NWayTestReg=0x70, - RxCnt=0x72, /* packet received counter */ - CSCR=0x74, /* chip status and configuration register */ - PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ - /* from 0x84 onwards are a number of power management/wakeup frame - * definitions we will probably never need to know about. */ -}; - -enum ChipCmdBits { - CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; - -/* Interrupt register bits, using my own meaningful names. */ -enum IntrStatusBits { - PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, - RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, - TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, -}; -enum TxStatusBits { - TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, - TxOutOfWindow=0x20000000, TxAborted=0x40000000, - TxCarrierLost=0x80000000, -}; -enum RxStatusBits { - RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, - RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, - RxBadAlign=0x0002, RxStatusOK=0x0001, -}; - -enum MediaStatusBits { - MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, - MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, -}; - -enum MIIBMCRBits { - BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, - BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, -}; - -enum CSCRBits { - CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, - CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, - CSCR_LinkDownCmd=0x0f3c0, -}; +/* Ethernet hardware address. */ +#define RTL_REG_MAC0 0x00 +/* Multicast filter. */ +#define RTL_REG_MAR0 0x08 +/* Transmit status (four 32bit registers). */ +#define RTL_REG_TXSTATUS0 0x10 +/* Tx descriptors (also four 32bit). */ +#define RTL_REG_TXADDR0 0x20 +#define RTL_REG_RXBUF 0x30 +#define RTL_REG_RXEARLYCNT 0x34 +#define RTL_REG_RXEARLYSTATUS 0x36 +#define RTL_REG_CHIPCMD 0x37 +#define RTL_REG_CHIPCMD_CMDRESET BIT(4) +#define RTL_REG_CHIPCMD_CMDRXENB BIT(3) +#define RTL_REG_CHIPCMD_CMDTXENB BIT(2) +#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0) +#define RTL_REG_RXBUFPTR 0x38 +#define RTL_REG_RXBUFADDR 0x3A +#define RTL_REG_INTRMASK 0x3C +#define RTL_REG_INTRSTATUS 0x3E +#define RTL_REG_INTRSTATUS_PCIERR BIT(15) +#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14) +#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13) +#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6) +#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5) +#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4) +#define RTL_REG_INTRSTATUS_TXERR BIT(3) +#define RTL_REG_INTRSTATUS_TXOK BIT(2) +#define RTL_REG_INTRSTATUS_RXERR BIT(1) +#define RTL_REG_INTRSTATUS_RXOK BIT(0) +#define RTL_REG_TXCONFIG 0x40 +#define RTL_REG_RXCONFIG 0x44 +#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7) +#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5) +#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4) +#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3) +#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2) +#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1) +#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0) +/* general-purpose counter. */ +#define RTL_REG_TIMER 0x48 +/* 24 bits valid, write clears. */ +#define RTL_REG_RXMISSED 0x4C +#define RTL_REG_CFG9346 0x50 +#define RTL_REG_CONFIG0 0x51 +#define RTL_REG_CONFIG1 0x52 +/* intr if gp counter reaches this value */ +#define RTL_REG_TIMERINTRREG 0x54 +#define RTL_REG_MEDIASTATUS 0x58 +#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7) +#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6) +#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3) +#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2) +#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1) +#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0) +#define RTL_REG_CONFIG3 0x59 +#define RTL_REG_MULTIINTR 0x5C +/* revision of the RTL8139 chip */ +#define RTL_REG_REVISIONID 0x5E +#define RTL_REG_TXSUMMARY 0x60 +#define RTL_REG_MII_BMCR 0x62 +#define RTL_REG_MII_BMSR 0x64 +#define RTL_REG_NWAYADVERT 0x66 +#define RTL_REG_NWAYLPAR 0x68 +#define RTL_REG_NWAYEXPANSION 0x6A +#define RTL_REG_DISCONNECTCNT 0x6C +#define RTL_REG_FALSECARRIERCNT 0x6E +#define RTL_REG_NWAYTESTREG 0x70 +/* packet received counter */ +#define RTL_REG_RXCNT 0x72 +/* chip status and configuration register */ +#define RTL_REG_CSCR 0x74 +#define RTL_REG_PHYPARM1 0x78 +#define RTL_REG_TWISTERPARM 0x7c +/* undocumented */ +#define RTL_REG_PHYPARM2 0x80 +/* + * from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. + */ -/* Bits in RxConfig. */ -enum rx_mode_bits { - RxCfgWrap=0x80, - AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, - AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, -}; +#define RTL_STS_RXMULTICAST BIT(15) +#define RTL_STS_RXPHYSICAL BIT(14) +#define RTL_STS_RXBROADCAST BIT(13) +#define RTL_STS_RXBADSYMBOL BIT(5) +#define RTL_STS_RXRUNT BIT(4) +#define RTL_STS_RXTOOLONG BIT(3) +#define RTL_STS_RXCRCERR BIT(2) +#define RTL_STS_RXBADALIGN BIT(1) +#define RTL_STS_RXSTATUSOK BIT(0) static int ioaddr; static unsigned int cur_rx,cur_tx; @@ -251,7 +270,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) ioaddr = dev->iobase; /* Bring the chip out of low-power mode. */ - outb(0x00, ioaddr + Config1); + outb(0x00, ioaddr + RTL_REG_CONFIG1); addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; for (i = 0; i < 3; i++) @@ -259,7 +278,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) rtl_reset(dev); - if (inb(ioaddr + MediaStatus) & MSRLinkFail) { + if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { printf("Cable not connected or other link failure\n"); return -1 ; } @@ -286,15 +305,15 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) #define eeprom_delay() inl(ee_addr) /* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) +#define EE_WRITE_CMD 5 +#define EE_READ_CMD 6 +#define EE_ERASE_CMD 7 static int read_eeprom(int location, int addr_len) { int i; unsigned int retval = 0; - long ee_addr = ioaddr + Cfg9346; + long ee_addr = ioaddr + RTL_REG_CFG9346; int read_cmd = location | (EE_READ_CMD << addr_len); outb(EE_ENB & ~EE_CS, ee_addr); @@ -335,41 +354,46 @@ static void set_rx_mode(struct eth_device *dev) { unsigned int mc_filter[2]; int rx_mode; /* !IFF_PROMISC */ - rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | + RTL_REG_RXCONFIG_ACCEPTMULTICAST | + RTL_REG_RXCONFIG_ACCEPTMYPHYS; mc_filter[1] = mc_filter[0] = 0xffffffff; - outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); + outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG); - outl(mc_filter[0], ioaddr + MAR0 + 0); - outl(mc_filter[1], ioaddr + MAR0 + 4); + outl(mc_filter[0], ioaddr + RTL_REG_MAR0 + 0); + outl(mc_filter[1], ioaddr + RTL_REG_MAR0 + 4); } static void rtl_reset(struct eth_device *dev) { int i; - outb(CmdReset, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); cur_rx = 0; cur_tx = 0; /* Give the chip 10ms to finish the reset. */ for (i=0; i<100; ++i){ - if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + if ((inb(ioaddr + RTL_REG_CHIPCMD) & + RTL_REG_CHIPCMD_CMDRESET) == 0) + break; udelay (100); /* wait 100us */ } for (i = 0; i < ETH_ALEN; i++) - outb(dev->enetaddr[i], ioaddr + MAC0 + i); + outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i); /* Must enable Tx/Rx before setting transfer thresholds! */ - outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, + ioaddr + RTL_REG_CHIPCMD); outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), - ioaddr + RxConfig); /* accept no frames yet! */ - outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); + ioaddr + RTL_REG_RXCONFIG); /* accept no frames yet! */ + outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG); - /* The Linux driver changes Config1 here to use a different LED pattern + /* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern * for half duplex or full/autodetect duplex (for full/autodetect, the * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses * TX/RX, Link100, Link10). This is messy, because it doesn't match @@ -380,24 +404,25 @@ static void rtl_reset(struct eth_device *dev) debug_cond(DEBUG_RX, "rx ring address is %lX\n",(unsigned long)rx_ring); flush_cache((unsigned long)rx_ring, RX_BUF_LEN); - outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF); - /* If we add multicast support, the MAR0 register would have to be + /* If we add multicast support, the RTL_REG_MAR0 register would have to be * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ - outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, + ioaddr + RTL_REG_CHIPCMD); - outl(rtl8139_rx_config, ioaddr + RxConfig); + outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); /* Start the chip's Tx and Rx process. */ - outl(0, ioaddr + RxMissed); + outl(0, ioaddr + RTL_REG_RXMISSED); /* set_rx_mode */ set_rx_mode(dev); /* Disable all known interrupts by setting the interrupt mask. */ - outw(0, ioaddr + IntrMask); + outw(0, ioaddr + RTL_REG_INTRMASK); } static int rtl_transmit(struct eth_device *dev, void *packet, int length) @@ -420,23 +445,32 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length) } flush_cache((unsigned long)tx_buffer, length); - outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl(phys_to_bus((int)tx_buffer), ioaddr + RTL_REG_TXADDR0 + cur_tx*4); outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, - ioaddr + TxStatus0 + cur_tx*4); + ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); do { - status = inw(ioaddr + IntrStatus); - /* Only acknlowledge interrupt sources we can properly handle - * here - the RxOverflow/RxFIFOOver MUST be handled in the - * rtl_poll() function. */ - outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); - if ((status & (TxOK | TxErr | PCIErr)) != 0) break; + status = inw(ioaddr + RTL_REG_INTRSTATUS); + /* + * Only acknlowledge interrupt sources we can properly + * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/ + * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the + * rtl_poll() function. + */ + outw(status & (RTL_REG_INTRSTATUS_TXOK | + RTL_REG_INTRSTATUS_TXERR | + RTL_REG_INTRSTATUS_PCIERR), + ioaddr + RTL_REG_INTRSTATUS); + if ((status & (RTL_REG_INTRSTATUS_TXOK | + RTL_REG_INTRSTATUS_TXERR | + RTL_REG_INTRSTATUS_PCIERR)) != 0) + break; udelay(10); } while (i++ < RTL_TIMEOUT); - txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); + txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4); - if (status & TxOK) { + if (status & RTL_REG_INTRSTATUS_TXOK) { cur_tx = (cur_tx + 1) % NUM_TX_DESC; debug_cond(DEBUG_TX, @@ -465,13 +499,16 @@ static int rtl_poll(struct eth_device *dev) ioaddr = dev->iobase; - if (inb(ioaddr + ChipCmd) & RxBufEmpty) { + if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) { return 0; } - status = inw(ioaddr + IntrStatus); + status = inw(ioaddr + RTL_REG_INTRSTATUS); /* See below for the rest of the interrupt acknowledges. */ - outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + outw(status & ~(RTL_REG_INTRSTATUS_RXFIFOOVER | + RTL_REG_INTRSTATUS_RXOVERFLOW | + RTL_REG_INTRSTATUS_RXOK), + ioaddr + RTL_REG_INTRSTATUS); debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status); @@ -481,7 +518,9 @@ static int rtl_poll(struct eth_device *dev) rx_size = rx_status >> 16; rx_status &= 0xffff; - if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || + if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT | + RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR | + RTL_STS_RXBADALIGN)) || (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { printf("rx error %hX\n", rx_status); rtl_reset(dev); /* this clears all interrupts still pending */ @@ -507,11 +546,13 @@ static int rtl_poll(struct eth_device *dev) flush_cache((unsigned long)rx_ring, RX_BUF_LEN); cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; - outw(cur_rx - 16, ioaddr + RxBufPtr); + outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR); /* See RTL8139 Programming Guide V0.1 for the official handling of * Rx overflow situations. The document itself contains basically no * usable information, except for a few exception handling rules. */ - outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + outw(status & (RTL_REG_INTRSTATUS_RXFIFOOVER | + RTL_REG_INTRSTATUS_RXOVERFLOW | + RTL_REG_INTRSTATUS_RXOK), ioaddr + RTL_REG_INTRSTATUS); return length; } @@ -522,11 +563,11 @@ static void rtl_disable(struct eth_device *dev) ioaddr = dev->iobase; /* reset the chip */ - outb(CmdReset, ioaddr + ChipCmd); + outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); /* Give the chip 10ms to finish the reset. */ for (i=0; i<100; ++i){ - if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break; udelay (100); /* wait 100us */ } }