| Message ID | 20200412085428.27519-8-biwen.li@oss.nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [01/27] rtc: ds1337: Add driver model support | expand |
>-----Original Message----- >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Biwen Li >Sent: Sunday, April 12, 2020 2:24 PM >To: Jagdish Gediya <jagdish.gediya at nxp.com>; Priyanka Jain ><priyanka.jain at nxp.com>; hs at denx.de; jagan at amarulasolutions.com; >aford173 at gmail.com; Alison Wang <alison.wang at nxp.com>; >jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1 at nxp.com>; >Rajesh Bhagat <rajesh.bhagat at nxp.com>; Ruchika Gupta ><ruchika.gupta at nxp.com>; olteanv at gmail.com >Cc: Xiaobo Xie <xiaobo.xie at nxp.com>; Jiafei Pan <jiafei.pan at nxp.com>; u- >boot at lists.denx.de; Z.q. Hou <zhiqiang.hou at nxp.com>; Biwen Li ><biwen.li at nxp.com> >Subject: [PATCH 08/27] dm: powerpc: P2020RDB: add i2c DM support > >From: Biwen Li <biwen.li at nxp.com> > >This supports i2c DM for board P2020RDB > >Signed-off-by: Biwen Li <biwen.li at nxp.com> >--- > arch/powerpc/dts/p2020-post.dtsi | 3 +++ > arch/powerpc/dts/p2020.dtsi | 2 +- > include/configs/p1_p2_rdb_pc.h | 2 +- > 3 files changed, 5 insertions(+), 2 deletions(-) > >diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020- >post.dtsi >index 5bbd5c5468..4ed093dad4 100644 >--- a/arch/powerpc/dts/p2020-post.dtsi >+++ b/arch/powerpc/dts/p2020-post.dtsi >@@ -37,6 +37,9 @@ > /* Filled in by U-Boot */ > clock-frequency = <0>; > }; >+ >+ /include/ "pq3-i2c-0.dtsi" >+ /include/ "pq3-i2c-1.dtsi" > }; > > /* PCIe controller base address 0x8000 */ diff --git >a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index >7c4c2061d4..13a4a51526 100644 >--- a/arch/powerpc/dts/p2020.dtsi >+++ b/arch/powerpc/dts/p2020.dtsi >@@ -3,7 +3,7 @@ > * P2020 Silicon/SoC Device Tree Source (pre include) > * > * Copyright 2013 Freescale Semiconductor Inc. >- * Copyright 2019 NXP >+ * Copyright 2019-2020 NXP > */ > > /dts-v1/; >diff --git a/include/configs/p1_p2_rdb_pc.h >b/include/configs/p1_p2_rdb_pc.h index 7089b69bf3..d59fd033bd 100644 >--- a/include/configs/p1_p2_rdb_pc.h >+++ b/include/configs/p1_p2_rdb_pc.h >@@ -538,8 +538,8 @@ > #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) > > /* I2C */ >+#ifndef CONFIG_DM_I2C > #define CONFIG_SYS_I2C >-#define CONFIG_SYS_I2C_FSL > #define CONFIG_SYS_FSL_I2C_SPEED 400000 > #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F > #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 >-- >2.17.1 This changes were supposed to be merged with a previous patch. We need to ensure that all patches are compiling independently successfully. Do run buildman test before submitting the next version of this patch set. Regards Priyanka
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 5bbd5c5468..4ed093dad4 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -37,6 +37,9 @@ /* Filled in by U-Boot */ clock-frequency = <0>; }; + + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index 7c4c2061d4..13a4a51526 100644 --- a/arch/powerpc/dts/p2020.dtsi +++ b/arch/powerpc/dts/p2020.dtsi @@ -3,7 +3,7 @@ * P2020 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 7089b69bf3..d59fd033bd 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -538,8 +538,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000