diff mbox series

[v3,10/19] video: mxsfb: enable setting HSYNC negative polarity

Message ID 20200408151025.20549-11-giulio.benetti@benettiengineering.com
State Superseded
Headers show
Series i.MXRT1050 add LCDIF support | expand

Commit Message

Giulio Benetti April 8, 2020, 3:10 p.m. UTC 
HSYNC signal can now be flipped according to display_flags bitmaks by
writing its bitmask on vdctrl0 register.

Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
---
 drivers/video/mxsfb.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

Comments

Anatolij Gustschin April 17, 2020, 6:18 p.m. UTC | #1 
On Wed,  8 Apr 2020 17:10:16 +0200
Giulio Benetti giulio.benetti at benettiengineering.com wrote:

> HSYNC signal can now be flipped according to display_flags bitmaks by
> writing its bitmask on vdctrl0 register.
> 
> Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>

Reviewed-by: Anatolij Gustschin <agust at denx.de>

--
Anatolij
Stefano Babic April 19, 2020, 9:08 a.m. UTC | #2 
> HSYNC signal can now be flipped according to display_flags bitmaks by
> writing its bitmask on vdctrl0 register.
> Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
> Reviewed-by: Anatolij Gustschin <agust at denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index cdd6dfaced..9912cf3d82 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -57,8 +57,10 @@  static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 			 struct display_timing *timings, int bpp)
 {
 	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	const enum display_flags flags = timings->flags;
 	uint32_t word_len = 0, bus_width = 0;
 	uint8_t valid_data = 0;
+	uint32_t vdctrl0;
 
 #if CONFIG_IS_ENABLED(CLK)
 	struct clk per_clk;
@@ -118,10 +120,14 @@  static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 		timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 
-	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
-		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
-		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
-		timings->vsync_len.typ, &regs->hw_lcdif_vdctrl0);
+	vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+		  LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+		  LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+		  timings->vsync_len.typ;
+
+	if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
+	writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 	writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 		timings->vsync_len.typ + timings->vactive.typ,
 		&regs->hw_lcdif_vdctrl1);