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[v4,13/31] x86: apl: Add Global NVS table header

Message ID 20200407210023.v4.13.I4aa2fe09882dcf5a040603469bac136e4342d350@changeid
State Superseded
Headers show
Series dm: Add programmatic generation of ACPI tables (part A) | expand

Commit Message

Simon Glass April 8, 2020, 3 a.m. UTC 
Add the C version of this header. It includes a few Chrome OS bits which
are disabled for a normal build.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Wolfgang Wallner <wolgang.wallner at br-automation.com>
---

Changes in v4:
- Fix indentation of unused
- Calculate the padding

Changes in v3:
- Fix stray #endif

Changes in v2:
- Drop the Chrome OS pieces
- Rename the 'coreboot' console to 'U-Boot'

 .../include/asm/arch-apollolake/global_nvs.h  | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/x86/include/asm/arch-apollolake/global_nvs.h

Comments

Andy Shevchenko April 8, 2020, 5:14 p.m. UTC | #1 
On Tue, Apr 07, 2020 at 09:00:49PM -0600, Simon Glass wrote:
> Add the C version of this header. It includes a few Chrome OS bits which
> are disabled for a normal build.

> +	u8	unused[0x100 - 0x3d];		/* Pad out to 0x100 */
> +	u8	unused2[0x1000 - 0x100];	/* Pad out to 4KB */

Inconsistent size representation in the comment: 256 bytes, 4096 bytes?
Also I would rather name unused1 and unused2.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h
new file mode 100644
index 00000000000..9351a008f2f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -0,0 +1,36 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2017 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ * Copyright Google LLC 2019
+ *
+ * Modified from coreboot apollolake/include/soc/nvs.h
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	/* Miscellaneous */
+	u8	pcnt; /* 0x00 - Processor Count */
+	u8	ppcm; /* 0x01 - Max PPC State */
+	u8	lids; /* 0x02 - LID State */
+	u8	pwrs; /* 0x03 - AC Power State */
+	u8	dpte; /* 0x04 - Enable DPTF */
+	u32	cbmc; /* 0x05 - 0x08 - U-Boot Console */
+	u64	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	u64	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	u64	nhla; /* 0x19 - 0x20 - NHLT Address */
+	u32	nhll; /* 0x21 - 0x24 - NHLT Length */
+	u32	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	u8	scdp; /* 0x29 - SD_CD GPIO portid */
+	u8	scdo; /* 0x2a - GPIO pad offset relative to the community */
+	u8	uior; /* 0x2b - UART debug controller init on S3 resume */
+	u8	ecps; /* 0x2c - SGX Enabled status */
+	u64	emna; /* 0x2d - 0x34 EPC base address */
+	u64	elng; /* 0x35 - 0x3c EPC Length */
+	u8	unused[0x100 - 0x3d];		/* Pad out to 0x100 */
+	u8	unused2[0x1000 - 0x100];	/* Pad out to 4KB */
+};
+
+#endif /* _GLOBAL_NVS_H_ */