From patchwork Sat Apr 4 05:16:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Akman X-Patchwork-Id: 237156 List-Id: U-Boot discussion From: sinan at writeme.com (sinan at writeme.com) Date: Sat, 4 Apr 2020 01:16:46 -0400 Subject: [PATCH v2 1/2] mpc8379erdb: Add device tree In-Reply-To: <2662dd1d-46ee-7c09-7fef-1053d3fec34d@samsung.com> References: <2662dd1d-46ee-7c09-7fef-1053d3fec34d@samsung.com> Message-ID: <20200404051647.10922-1-sinan@writeme.com> From: Sinan Akman Signed-off-by: Sinan Akman --- Changes for v2: - Split patches for device tree and DM_MMC arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/mpc8379erdb.dts | 74 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/powerpc/dts/mpc8379erdb.dts -- 2.14.5 diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c..e3ec033096 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts new file mode 100644 index 0000000000..b1881b161c --- /dev/null +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8379E RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/ { + compatible = "fsl,mpc8379erdb"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8379 at 0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; // 256MB at 0 + }; + + localbus at e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + }; + + immr at e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + sdhc at 2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + bus-width = <0x4>; + clock-frequency = <0>; + }; + + ipic: interrupt-controller at 700 { + compatible = "fsl,ipic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + }; + +};