From patchwork Fri Apr 3 09:25:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 237141 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Fri, 3 Apr 2020 11:25:37 +0200 Subject: [PATCH v2 2/2] arm: stm32mp: activate data cache on DDR in SPL In-Reply-To: <20200403092537.19961-1-patrick.delaunay@st.com> References: <20200403092537.19961-1-patrick.delaunay@st.com> Message-ID: <20200403105644.v2.2.Ib571c64a8c50fcbe386e728e38bbd320427e4efb@changeid> Activate cache on DDR to improves the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Signed-off-by: Patrick Delaunay --- Changes in v2: - new arch/arm/mach-stm32mp/spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 9cd7b418a4..279121af75 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -117,4 +118,24 @@ void board_init_f(ulong dummy) printf("DRAM init failed: %d\n", ret); hang(); } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); + debug("SPL bye\n"); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); + debug("SPL bye\n"); }