| Message ID | 20200403105644.v2.2.Ib571c64a8c50fcbe386e728e38bbd320427e4efb@changeid |
|---|---|
| State | New |
| Headers | show |
| Series | arm: stm32mp1: activate data cache in SPL and before relocation | expand |
On 4/3/20 11:25 AM, Patrick Delaunay wrote: > Activate cache on DDR to improves the accesses to DDR used by SPL: > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, > to avoid speculative access and issue in get_ram_size(). > Data cache is deactivated at the end of SPL, to flush the data cache > and the TLB. > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > --- > > Changes in v2: > - new > > arch/arm/mach-stm32mp/spl.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c > index 9cd7b418a4..279121af75 100644 > --- a/arch/arm/mach-stm32mp/spl.c > +++ b/arch/arm/mach-stm32mp/spl.c > @@ -4,6 +4,7 @@ > */ > > #include <common.h> > +#include <cpu_func.h> > #include <dm.h> > #include <hang.h> > #include <spl.h> > @@ -117,4 +118,24 @@ void board_init_f(ulong dummy) > printf("DRAM init failed: %d\n", ret); > hang(); > } > + > + /* > + * activate cache on DDR only when DDR is fully initialized > + * to avoid speculative access and issue in get_ram_size() > + */ > + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) > + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, > + DCACHE_DEFAULT_OPTION); > +} > + > +void spl_board_prepare_for_boot(void) > +{ > + dcache_disable(); > + debug("SPL bye\n"); > +} > + > +void spl_board_prepare_for_boot_linux(void) > +{ > + dcache_disable(); > + debug("SPL bye\n"); Is the debug() statement really needed ? I think the common SPL code already has some.
Dear Marek, > From: Marek Vasut <marex at denx.de> > Sent: vendredi 3 avril 2020 23:33 > > On 4/3/20 11:25 AM, Patrick Delaunay wrote: > > Activate cache on DDR to improves the accesses to DDR used by SPL: > > - CONFIG_SPL_BSS_START_ADDR > > - CONFIG_SYS_SPL_MALLOC_START > > > > Cache is configured only when DDR is fully initialized, to avoid > > speculative access and issue in get_ram_size(). > > Data cache is deactivated at the end of SPL, to flush the data cache > > and the TLB. > > > > Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> > > --- > > > > Changes in v2: > > - new > > [...] > > +void spl_board_prepare_for_boot(void) { > > + dcache_disable(); > > + debug("SPL bye\n"); > > +} > > + > > +void spl_board_prepare_for_boot_linux(void) > > +{ > > + dcache_disable(); > > + debug("SPL bye\n"); > > Is the debug() statement really needed ? I think the common SPL code already > has some. Not needed, I will drop them in V3. Patrick
On 4/9/20 8:10 PM, Patrick DELAUNAY wrote: > Dear Marek, > >> From: Marek Vasut <marex at denx.de> >> Sent: vendredi 3 avril 2020 23:33 >> >> On 4/3/20 11:25 AM, Patrick Delaunay wrote: >>> Activate cache on DDR to improves the accesses to DDR used by SPL: >>> - CONFIG_SPL_BSS_START_ADDR >>> - CONFIG_SYS_SPL_MALLOC_START >>> >>> Cache is configured only when DDR is fully initialized, to avoid >>> speculative access and issue in get_ram_size(). >>> Data cache is deactivated at the end of SPL, to flush the data cache >>> and the TLB. >>> >>> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> >>> --- >>> >>> Changes in v2: >>> - new >>> > > [...] > >>> +void spl_board_prepare_for_boot(void) { >>> + dcache_disable(); >>> + debug("SPL bye\n"); >>> +} >>> + >>> +void spl_board_prepare_for_boot_linux(void) >>> +{ >>> + dcache_disable(); >>> + debug("SPL bye\n"); >> >> Is the debug() statement really needed ? I think the common SPL code already >> has some. > > Not needed, I will drop them in V3. Thanks
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 9cd7b418a4..279121af75 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <hang.h> #include <spl.h> @@ -117,4 +118,24 @@ void board_init_f(ulong dummy) printf("DRAM init failed: %d\n", ret); hang(); } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); + debug("SPL bye\n"); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); + debug("SPL bye\n"); }
Activate cache on DDR to improves the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> --- Changes in v2: - new arch/arm/mach-stm32mp/spl.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)