| Message ID | 20200329170538.25449-15-pragnesh.patel@sifive.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 56a45371d4..8f6c9f525d 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -73,3 +73,7 @@ &qspi2 { u-boot,dm-spl; }; + +&l2cache { + status = "okay"; +};
Add L2 cache node to enable cache ways from U-Boot Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com> --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)