From patchwork Tue Mar 24 08:12:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 244202 List-Id: U-Boot discussion From: Zhiqiang.Hou at nxp.com (Zhiqiang Hou) Date: Tue, 24 Mar 2020 16:12:04 +0800 Subject: [PATCHv2 4/9] board: lx2160a: Make sure the RD tables address align to 64KB In-Reply-To: <20200324081209.48449-1-Zhiqiang.Hou@nxp.com> References: <20200324081209.48449-1-Zhiqiang.Hou@nxp.com> Message-ID: <20200324081209.48449-5-Zhiqiang.Hou@nxp.com> From: Hou Zhiqiang As the lower 16bit of the redistributor pending table is reserved for describing the memory attributes, we must give a 64KB aligned address to the GIC LPI initialization function. Signed-off-by: Hou Zhiqiang --- V2: - The #5 of v1 patchset. board/freescale/lx2160a/lx2160a.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 7f22110dc6..c8e962ce3d 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -678,7 +679,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #ifdef CONFIG_GIC_V3_ITS - gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE; + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base); if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores())) debug("%s: failed to init gic-lpi-tables\n", __func__);