diff mbox series

[v2,01/19] clk: imx: pllv3: add enable_bit

Message ID 20200322224435.114512-2-giulio.benetti@benettiengineering.com
State Accepted
Commit 8cefbe98b16e756b886ebcbe77ba66e05b9392b4
Headers show
Series i.MXRT1050 add LCDIF support | expand

Commit Message

Giulio Benetti March 22, 2020, 10:44 p.m. UTC 
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.

Signed-off-by: Giulio Benetti <giulio.benetti at benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma at denx.de>
---
 drivers/clk/imx/clk-pllv3.c | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 525442debf..b4a9d587e1 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -25,6 +25,7 @@ 
 #define PLL_DENOM_OFFSET	0x20
 
 #define BM_PLL_POWER		(0x1 << 12)
+#define BM_PLL_ENABLE		(0x1 << 13)
 #define BM_PLL_LOCK		(0x1 << 31)
 
 struct clk_pllv3 {
@@ -32,6 +33,7 @@  struct clk_pllv3 {
 	void __iomem	*base;
 	u32		power_bit;
 	bool		powerup_set;
+	u32		enable_bit;
 	u32		div_mask;
 	u32		div_shift;
 };
@@ -83,6 +85,9 @@  static int clk_pllv3_generic_enable(struct clk *clk)
 		val |= pll->power_bit;
 	else
 		val &= ~pll->power_bit;
+
+	val |= pll->enable_bit;
+
 	writel(val, pll->base);
 
 	return 0;
@@ -98,6 +103,9 @@  static int clk_pllv3_generic_disable(struct clk *clk)
 		val &= ~pll->power_bit;
 	else
 		val |= pll->power_bit;
+
+	val &= ~pll->enable_bit;
+
 	writel(val, pll->base);
 
 	return 0;
@@ -238,6 +246,7 @@  struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 		return ERR_PTR(-ENOMEM);
 
 	pll->power_bit = BM_PLL_POWER;
+	pll->enable_bit = BM_PLL_ENABLE;
 
 	switch (type) {
 	case IMX_PLLV3_GENERIC: